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Tue, 10 Nov 2026 03:22:09 -0800 (PST) Received: from localhost ([2001:19f0:8000:3bef:5400:6ff:fef9:667]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3b1678d1c0csm3413913a91.6.2026.11.10.03.22.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Nov 2026 03:22:09 -0800 (PST) Date: Tue, 10 Nov 2026 19:21:50 +0800 From: Inochi Amaoto To: Krzysztof Kozlowski , Inochi Amaoto , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Minas Harutyunyan , Greg Kroah-Hartman , Longbin Li , Dinh Nguyen , Paul Zimmerman , Felipe Balbi Cc: devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, Yixun Lan Subject: Re: [PATCH 4/4] riscv: dts: sophgo: Enable USB role switch on Huashan PI Message-ID: References: <20261110070627.217946-1-inochiama@gmail.com> <20261110070627.217946-5-inochiama@gmail.com> <2e878ad2-1a20-4ee7-8460-64e0d9774ff5@kernel.org> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <2e878ad2-1a20-4ee7-8460-64e0d9774ff5@kernel.org> On Tue, Nov 10, 2026 at 11:41:37AM +0100, Krzysztof Kozlowski wrote: > On 10/11/2026 08:06, Inochi Amaoto wrote: > > As current the DWC2 support role switch on CV18XX SoCs. Enable it > > on Huashan PI. > > > > Signed-off-by: Inochi Amaoto > > --- > > arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts | 4 +++- > > 1 file changed, 3 insertions(+), 1 deletion(-) > > DTS cannot be combined in this patchset and must be split. Don't mix > patches from independent subsystems when you send something explicitly > targeting only one subsystem. > See also: Documentation/devicetree/bindings/submitting-patches.rst > > > Best regards, > Krzysztof Sorry for this mistake, I will spilt them in the next patch. Thanks. Regards, Inochi