From: Adrian Hunter <adrian.hunter-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
To: Ritesh Harjani <riteshh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
ulf.hansson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org,
linux-mmc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org
Cc: david.brown-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org,
andy.gross-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
georgi.djakov-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org,
alex.lemberg-XdAiOPVOjttBDgjK7y7TUQ@public.gmane.org,
mateusz.nowak-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org,
Yuliy.Izrailov-XdAiOPVOjttBDgjK7y7TUQ@public.gmane.org,
asutoshd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
david.griego-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org,
stummala-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
venkatg-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org,
pramod.gurav-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org
Subject: Re: [PATCH v5 08/12] mmc: sdhci-msm: Add clock changes for DDR mode.
Date: Mon, 10 Oct 2016 13:26:46 +0300 [thread overview]
Message-ID: <b088db75-2b51-5038-038b-f7110f762f73@intel.com> (raw)
In-Reply-To: <1475678440-3525-9-git-send-email-riteshh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
On 05/10/16 17:40, Ritesh Harjani wrote:
> SDHC MSM controller need 2x clock for MCLK at GCC.
> Hence make required changes to have 2x clock for
> DDR timing modes.
>
> Signed-off-by: Ritesh Harjani <riteshh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Acked-by: Adrian Hunter <adrian.hunter-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
> ---
> drivers/mmc/host/sdhci-msm.c | 25 ++++++++++++++++++++-----
> 1 file changed, 20 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
> index 9d18cf0..eb1a9e3 100644
> --- a/drivers/mmc/host/sdhci-msm.c
> +++ b/drivers/mmc/host/sdhci-msm.c
> @@ -669,6 +669,7 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
> {
> struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
> + struct mmc_ios curr_ios = host->mmc->ios;
> u32 msm_clock;
> int rc;
>
> @@ -676,15 +677,29 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
> goto out;
>
> spin_unlock_irq(&host->lock);
> - if ((clock != msm_host->clk_rate) && msm_host->clk_table) {
> - msm_clock = sdhci_msm_get_msm_clk_rate(host, clock);
> + if (((curr_ios.timing == MMC_TIMING_UHS_DDR50) ||
> + (curr_ios.timing == MMC_TIMING_MMC_DDR52) ||
> + (curr_ios.timing == MMC_TIMING_MMC_HS400)) &&
> + msm_host->clk_table) {
> + /*
> + * The SDHC requires internal clock frequency to be double the
> + * actual clock that will be set for DDR mode. The controller
> + * uses the faster clock(100/400MHz) for some of its parts and
> + * send the actual required clock (50/200MHz) to the card.
> + */
> + clock *= 2;
> + }
> + msm_clock = sdhci_msm_get_msm_clk_rate(host, clock);
> +
> + if ((msm_clock != msm_host->clk_rate) && msm_host->clk_table) {
> rc = clk_set_rate(msm_host->clk, msm_clock);
> if (rc) {
> - pr_err("%s: failed to set clock at rate %u, requested clock rate %u\n",
> - mmc_hostname(host->mmc), msm_clock, clock);
> + pr_err("%s: failed to set clock at rate %u at timing %d\n",
> + mmc_hostname(host->mmc), msm_clock,
> + curr_ios.timing);
> goto out;
> }
> - msm_host->clk_rate = clock;
> + msm_host->clk_rate = msm_clock;
> pr_debug("%s: setting clock at rate %lu\n",
> mmc_hostname(host->mmc), clk_get_rate(msm_host->clk));
> }
>
--
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next prev parent reply other threads:[~2016-10-10 10:26 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-05 14:40 [PATCH v5 00/12] mmc: sdhci-msm: Add clk-rates, DDR, HS400 support Ritesh Harjani
2016-10-05 14:40 ` [PATCH v5 03/12] mmc: sdhci-msm: add pltfm_data support to get clk-rates from DT Ritesh Harjani
2016-10-10 9:35 ` Adrian Hunter
[not found] ` <7e5c2bfe-0a67-71e2-d083-49d9a712482e-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
2016-10-10 11:00 ` Ritesh Harjani
[not found] ` <1475678440-3525-4-git-send-email-riteshh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2016-10-10 12:57 ` Rob Herring
2016-10-10 16:07 ` Ritesh Harjani
2016-10-10 19:29 ` Rob Herring
2016-10-11 9:06 ` Ritesh Harjani
2016-10-11 12:31 ` Rob Herring
2016-11-07 11:21 ` Ritesh Harjani
2016-10-05 14:40 ` [PATCH v5 04/12] ARM: dts: qcom: Add clk-rates to sdhc1 & sdhc2 Ritesh Harjani
2016-10-05 14:40 ` [PATCH v5 05/12] mmc: sdhci-msm: Add get_min_clock() and get_max_clock() callback Ritesh Harjani
2016-10-10 9:46 ` Adrian Hunter
2016-10-10 11:05 ` Ritesh Harjani
2016-10-05 14:40 ` [PATCH v5 06/12] mmc: sdhci-msm: Enable few quirks Ritesh Harjani
2016-10-05 14:40 ` [PATCH v5 07/12] mmc: sdhci-msm: Implement set_clock callback for sdhci-msm Ritesh Harjani
[not found] ` <1475678440-3525-8-git-send-email-riteshh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2016-10-10 10:16 ` Adrian Hunter
2016-10-10 10:23 ` Adrian Hunter
[not found] ` <d35224cf-52e0-5ccc-9596-1c338df41c36-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
2016-10-10 11:17 ` Ritesh Harjani
2016-10-05 14:40 ` [PATCH v5 08/12] mmc: sdhci-msm: Add clock changes for DDR mode Ritesh Harjani
[not found] ` <1475678440-3525-9-git-send-email-riteshh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2016-10-10 10:26 ` Adrian Hunter [this message]
2016-10-05 14:40 ` [PATCH v5 09/12] arm64: dts: qcom: msm8916: Add ddr support to sdhc1 Ritesh Harjani
[not found] ` <1475678440-3525-1-git-send-email-riteshh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2016-10-05 14:40 ` [PATCH v5 01/12] mmc: sdhci-msm: Change poor style writel/readl of registers Ritesh Harjani
2016-10-05 14:40 ` [PATCH v5 02/12] mmc: sdhci-msm: Update DLL reset sequence Ritesh Harjani
2016-10-05 14:40 ` [PATCH v5 10/12] mmc: sdhci-msm: Add HS400 platform support Ritesh Harjani
2016-10-10 12:08 ` Adrian Hunter
2016-10-10 15:26 ` Ritesh Harjani
2016-10-05 14:40 ` [PATCH v5 11/12] mmc: sdhci-msm: Add calibration tuning for CDCLP533 circuit Ritesh Harjani
2016-10-10 12:49 ` Adrian Hunter
[not found] ` <183c2e6a-179b-b042-aef9-d1e5cb90b17d-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
2016-10-10 15:42 ` Ritesh Harjani
[not found] ` <6993d3a2-7961-2507-60d2-153c14e0bc17-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2016-10-11 6:39 ` Adrian Hunter
2016-10-11 9:09 ` Ritesh Harjani
2016-10-05 14:40 ` [PATCH v5 12/12] sdhci: sdhci-msm: update dll configuration Ritesh Harjani
2016-10-10 13:27 ` Adrian Hunter
2016-10-10 15:54 ` Ritesh Harjani
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