From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C5ECC14A4CC; Mon, 9 Dec 2024 05:26:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733722017; cv=none; b=orQFSIUsLGY81V0pA/Mz9CCbETaGJyAopWn2JnP/Rd4gldSa//2Jsqr4rTamcyBEdxRG5DlJ+ge8gR3uH68nqjj6rWJvDE8mimihiyEB/1nX4WWbc+8Fu+iy6WDqtq7zr0ATXKbXgNmSxR28fSfkk0w4lmbIyKjPnKMEpbcmXTs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733722017; c=relaxed/simple; bh=r3GRkniscda1h2jGia96dSzPLBBeCAFfWtcoKtCndGQ=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=i3Ey/5CcDlDfGyEizT1G2idsi5seVhNVvN4f2eemWSNTCyhYgCwH24FybAjm3ogBTLAOwEDgSVyZYw7/oIXwddF68DhoSeVDD+cYd2il5KaxqUS+Dtv1twoVbuFaov6g+zg16BMa3STX7KXCp2WTBOFjKac8EQdulgsJnlwqTxM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ideasonboard.com; spf=pass smtp.mailfrom=ideasonboard.com; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b=MNcFaGRJ; arc=none smtp.client-ip=213.167.242.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="MNcFaGRJ" Received: from [192.168.88.20] (91-157-155-49.elisa-laajakaista.fi [91.157.155.49]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id D15D4502; Mon, 9 Dec 2024 06:26:12 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1733721974; bh=r3GRkniscda1h2jGia96dSzPLBBeCAFfWtcoKtCndGQ=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=MNcFaGRJBul5yuH7NaP0tg2XJDSNmygMpCc4b5I+kzpZhFdf/+jqvsUrjcomDAGgW HMcuw98tx6rcyZZu/0v8bh6E2hdpABQr8j3h+Tq0uBkEBW1Ay7jABVRJQRgvzqYonB l3zuGGhsdXifB0AVrFn5g9BgwC7qQkiJrDXnZk9M= Message-ID: Date: Mon, 9 Dec 2024 07:26:41 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 05/10] clk: renesas: r8a779h0: Add display clocks To: Geert Uytterhoeven Cc: Laurent Pinchart , Kieran Bingham , Andrzej Hajda , Neil Armstrong , Robert Foss , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Michael Turquette , Stephen Boyd , LUU HOAI , Jagan Teki , Sam Ravnborg , Biju Das , dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Laurent Pinchart , linux-clk@vger.kernel.org, Tomi Valkeinen References: <20241206-rcar-gh-dsi-v3-0-d74c2166fa15@ideasonboard.com> <20241206-rcar-gh-dsi-v3-5-d74c2166fa15@ideasonboard.com> Content-Language: en-US From: Tomi Valkeinen Autocrypt: addr=tomi.valkeinen@ideasonboard.com; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi, On 06/12/2024 15:43, Geert Uytterhoeven wrote: > Hi Tomi, > > On Fri, Dec 6, 2024 at 10:33 AM Tomi Valkeinen > wrote: >> From: Tomi Valkeinen >> >> Add display related clocks for DU, DSI, FCPVD, and VSPD. >> >> Signed-off-by: Tomi Valkeinen >> Reviewed-by: Laurent Pinchart >> Tested-by: Geert Uytterhoeven > > Reviewed-by: Geert Uytterhoeven > i.e. will queue in renesas-clk for v6.14. > >> --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c >> +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c >> @@ -179,6 +179,9 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = { >> DEF_MOD("canfd0", 328, R8A779H0_CLK_SASYNCPERD2), >> DEF_MOD("csi40", 331, R8A779H0_CLK_CSI), >> DEF_MOD("csi41", 400, R8A779H0_CLK_CSI), >> + DEF_MOD("dis0", 411, R8A779H0_CLK_S0D3), >> + DEF_MOD("dsitxlink0", 415, R8A779H0_CLK_DSIREF), >> + DEF_MOD("fcpvd0", 508, R8A779H0_CLK_S0D3), >> DEF_MOD("hscif0", 514, R8A779H0_CLK_SASYNCPERD1), >> DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1), >> DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1), >> @@ -227,6 +230,7 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = { >> DEF_MOD("vin15", 811, R8A779H0_CLK_S0D4_VIO), >> DEF_MOD("vin16", 812, R8A779H0_CLK_S0D4_VIO), >> DEF_MOD("vin17", 813, R8A779H0_CLK_S0D4_VIO), >> + DEF_MOD("vspd0", 830, R8A779H0_CLK_S0D1_VIO), >> DEF_MOD("wdt1:wdt0", 907, R8A779H0_CLK_R), >> DEF_MOD("cmt0", 910, R8A779H0_CLK_R), >> DEF_MOD("cmt1", 911, R8A779H0_CLK_R), > > As mentioned by Laurent during his review on v1, all clock parents > should probably be some form of R8A779H0_CLK_S0Dx_VIO. > So I'm inclined to replace all of them by R8A779H0_CLK_VIOBUSD2 while > applying, which would match R-Car V4H. What do you mean with the above? First you say the clock parents should be some form of S0Dx_VIO, but then you say you'll use VIOBUSD2. Aren't those unrelated clocks, from different PLLs? > Are you OK with that? I'm fine with that. I can't really get much out of the docs wrt. clocking, and the clocks I used were from the BSP. Afaics, it looks similar to V4H, so it's probably best have the same clocks, as you suggest. Tomi