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Tue, 28 Jan 2025 09:56:00 -0800 (PST) Received: from [10.67.48.245] ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-2b28f16aa2bsm3683130fac.13.2025.01.28.09.55.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 28 Jan 2025 09:56:00 -0800 (PST) Message-ID: Date: Tue, 28 Jan 2025 09:55:57 -0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 -next 03/11] irqchip: Add Broadcom bcm2712 MSI-X interrupt controller To: Thomas Gleixner , Stanimir Varbanov , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Broadcom internal kernel review list , Bjorn Helgaas , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jim Quinlan , Nicolas Saenz Julienne , Lorenzo Pieralisi , Philipp Zabel , Andrea della Porta , Phil Elwell , Jonathan Bell , Dave Stevenson References: <20250120130119.671119-1-svarbanov@suse.de> <20250120130119.671119-4-svarbanov@suse.de> <87bjvs86w8.ffs@tglx> Content-Language: en-US From: Florian Fainelli Autocrypt: addr=florian.fainelli@broadcom.com; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 1/27/25 10:10, Thomas Gleixner wrote: > On Mon, Jan 20 2025 at 15:01, Stanimir Varbanov wrote: > >> Add an interrupt controller driver for MSI-X Interrupt Peripheral (MIP) >> hardware block found in bcm2712. The interrupt controller is used to >> handle MSI-X interrupts from peripherials behind PCIe endpoints like >> RP1 south bridge found in RPi5. >> >> There are two MIPs on bcm2712, the first has 64 consecutive SPIs >> assigned to 64 output vectors, and the second has 17 SPIs, but only >> 8 of them are consecutive starting at the 8th output vector. >> >> Signed-off-by: Stanimir Varbanov > > Reviewed-by: Thomas Gleixner > > As this is a new controller and required for the actual PCI muck, I > think the best way is to take it through the PCI tree, unless someone > wants me to pick the whole lot up. Agreed, the PCI maintainers should take patches 1 through 9 inclusive, and I will take patches 10-11 through the Broadcom ARM SoC tree, Bjorn, KW, does that work? -- Florian