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Mon, 06 Jul 2026 13:06:18 -0700 (PDT) X-Received: by 2002:a17:90b:2888:b0:35f:bb17:39f with SMTP id 98e67ed59e1d1-38112066822mr17984531a91.1.1783368377972; Mon, 06 Jul 2026 13:06:17 -0700 (PDT) Received: from [192.168.1.9] ([106.222.230.254]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-311747f5982sm47949eec.5.2026.07.06.13.06.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 06 Jul 2026 13:06:17 -0700 (PDT) Message-ID: Date: Tue, 7 Jul 2026 01:36:07 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 5/8] arm64: dts: qcom: Add GPU support for Kaanapali To: Konrad Dybcio Cc: Sean Paul , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Dmitry Baryshkov , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter References: <20260705-kaana-gpu-dt-v2-0-6ac53de56314@oss.qualcomm.com> <20260705-kaana-gpu-dt-v2-5-6ac53de56314@oss.qualcomm.com> From: Akhil P Oommen Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: Idr0M57NBuzl3dsOQh3WFkrnYK5FGMam X-Proofpoint-Spam-Info: AW1haW4tMjYwNzA2MDIwMiBTYWx0ZWRfX95Tusyu3qNiE oeoBsxsFxhhcKSEcAGHc6fY6mIDb4xVyRnBiHOuJU0Rb/2PsfwoF+TC1bKigRjvZwZsxiy+BxTK Mo2UZkCRjk/+uyk/a86WzFeALohjiW8= X-Authority-Analysis: v=2.4 cv=EPU2FVZC c=1 sm=1 tr=0 ts=6a4c0abb cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=fsdq8dFr2Uux402FS9br8A==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=ZaZH7ke036cbytEKeQwA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzA2MDIwMiBTYWx0ZWRfX9V694H+usSkx HLsfpl0S72oqiYU9zIQNlWL12HGhItGeuteO1Eg9KcmHlst6jQmtX4pQsROXd6SvxLpcerQnOMR dctgc8yGfQNAEQDIAKpcUNa79kIRb7iTplrbQ95OhONzdQPa0nGrm1L9WONkoqObBZEI+woe7Cz /xJQMs9wgJQuq2+CpQyBcotNDuf9HbiOCscr2IuF9oHngr+BCBPGAlSqzMcE2Fhs/I7Mnek9NxI AhiV73W2ue/nhg+pNsr0jqmNWGaCJrrsCQRY5qI2RcND1ql0D/OjfjdbeYfM9lxrAeN/2ObZb4k ZVj+Oybz00F8GQxby3LEWxEzXXDJrLLp/G+51xwN79IDxByg0E6VRJRYqWv2pmHmjqaJeZu594H E8px8y8lhjAmXLZV2Ds9+LpHuC3MPoS9IyT4+QQNOhhO797CrsO6c7kU6tbiRE6EFNEF2sr4w05 o6wF1eadbD2krGP+YaA== X-Proofpoint-ORIG-GUID: Idr0M57NBuzl3dsOQh3WFkrnYK5FGMam X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-06_02,2026-07-06_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 malwarescore=0 spamscore=0 adultscore=0 suspectscore=0 phishscore=0 bulkscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607060202 On 7/6/2026 3:07 PM, Konrad Dybcio wrote: > On 7/5/26 10:00 AM, Akhil P Oommen wrote: >> Adreno 840 present in Kaanapali SoC is the second generation GPU in >> A8x family. It is based on the new slice architecture with 3 slices, >> higher GMEM/caches etc. >> >> There is some re-arrangement in the reglist to properly cover maximum >> register region. Other than this, the DT description is mostly similar >> to the existing chipsets except the OPP tables. >> >> Reviewed-by: Dmitry Baryshkov >> Signed-off-by: Akhil P Oommen >> --- > > [...] > >> + qcom,gmu = <&gmu>; >> + #cooling-cells = <2>; >> + >> + nvmem-cells = <&gpu_speed_bin>; >> + nvmem-cell-names = "speed_bin"; > > This looks good to me, but I thought that on a8x, we're supposed to use > the freq limiting register in CX_MISC - is either of them preferred? > Or are they just hardwired to the same thing by chance I believe the other register would work, but I don't have a fused hw to test. OTOH, this is what is commercialized. Btw, the CX_MISC register is not present in all A8x GPUs, for eg: Pakala. -Akhil. > > Konrad