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Tue, 01 Jul 2025 12:36:27 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 561CaR4m032439 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 1 Jul 2025 12:36:27 GMT Received: from [10.235.9.75] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 1 Jul 2025 05:36:21 -0700 Message-ID: Date: Tue, 1 Jul 2025 20:36:19 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 7/8] arm64: dts: qcom: ipq5424: Add NSS clock controller node To: Konrad Dybcio , Bjorn Andersson , Michael Turquette , "Stephen Boyd" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Georgi Djakov , Philipp Zabel , Richard Cochran , Konrad Dybcio , "Catalin Marinas" , Will Deacon , Anusha Rao CC: , , , , , , , , , , , References: <20250627-qcom_ipq5424_nsscc-v2-0-8d392f65102a@quicinc.com> <20250627-qcom_ipq5424_nsscc-v2-7-8d392f65102a@quicinc.com> Content-Language: en-US From: Luo Jie In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=ZKfXmW7b c=1 sm=1 tr=0 ts=6863d64b cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=wZv0aL5qe_EQj9OG14cA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzAxMDA3OCBTYWx0ZWRfXxZa597Slz5L9 AmdpGrCIOpOtlppRjkZRcFzAdwk3GYMOh5n5ejywGCXzNDOqiWc4XSTbX2KSfeEC+cJserz+OOG xE/4H9i4Yu7N68/WGQq+K9L97KsygEckzeREJUoLwTbJV7dDh8z4BoEeukYw7YU4TmfY1AXEp3l gM5rKuubfnO8fT8FBvyIU34pLpfX9rabQQIEVcDzTJiWpfU+ORqcmUej6dHME+lDCHaS8QtoKsw PiNew8V/KcczMterynlIh+JUy48cdv/TJwCd5oCIABZU/NZ6W3nf639+Tw6e3j9jqS4J+b98Qwr tEiuv4HZQOC/PyYIwY+GxHWXje8MkkvGmvOzrWDThI2oSmprzlhacNFN8f5wGjmR7DvOYasdD7O fDToPB8HvUM1sLnY1vfSr3tAJQ1E81Tjy3Sb8KTL/DSXYvp1+n+AvpdKy30+eSvVZh0pcNk8 X-Proofpoint-ORIG-GUID: n4wJd_yJgHq0Rsmgt5mIYaEvtlb0yQJq X-Proofpoint-GUID: n4wJd_yJgHq0Rsmgt5mIYaEvtlb0yQJq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-01_02,2025-06-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxscore=0 mlxlogscore=999 spamscore=0 suspectscore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 impostorscore=0 malwarescore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507010078 On 7/1/2025 8:10 PM, Konrad Dybcio wrote: > > > On 01-Jul-25 14:08, Luo Jie wrote: >> >> >> On 6/28/2025 12:27 AM, Konrad Dybcio wrote: >>> On 6/27/25 2:09 PM, Luo Jie wrote: >>>> NSS clock controller provides the clocks and resets to the networking >>>> hardware blocks on the IPQ5424, such as PPE (Packet Process Engine) and >>>> UNIPHY (PCS) blocks. >>>> >>>> Signed-off-by: Luo Jie >>>> --- >>>>   arch/arm64/boot/dts/qcom/ipq5424.dtsi | 30 ++++++++++++++++++++++++++++++ >>>>   1 file changed, 30 insertions(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi >>>> index 2eea8a078595..eb4aa778269c 100644 >>>> --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi >>>> +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi >>>> @@ -730,6 +730,36 @@ frame@f42d000 { >>>>               }; >>>>           }; >>>>   +        clock-controller@39b00000 { >>>> +            compatible = "qcom,ipq5424-nsscc"; >>>> +            reg = <0 0x39b00000 0 0x800>; >>> >>> size = 0x100_000 >>> >>> with that: >>> >>> Reviewed-by: Konrad Dybcio >>> >>> Konrad >> >> I initially thought that a block size of 0x800 would be sufficient, as >> it covers the maximum address range needed for the clock configurations. >> However, the NSS clock controller block actually occupies an address >> range of 0x80000. I will update this to 0x80000 in the next version. >> Thank you for your feedback. > > 0x80_000 excludes the wrapper region. Please mark it as the entire > 0x100_000 that it occupies, no matter if there's anything in there > > Konrad I will update the register region to use the full 0x100_000 range to cover the entire area, including the wrapper region, as suggested, thanks.