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([2001:818:ea8e:7f00:2575:914:eedd:620e]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec366a699sm15116095e9.38.2025.04.03.04.15.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Apr 2025 04:15:28 -0700 (PDT) Message-ID: Subject: Re: [PATCH v3 2/3] dt-bindings: iio: dac: Add adi,ad3530r.yaml From: Nuno =?ISO-8859-1?Q?S=E1?= To: Kim Seer Paller , Jonathan Cameron , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Date: Thu, 03 Apr 2025 12:15:28 +0100 In-Reply-To: <20250403-togreg-v3-2-d4b06a4af5a9@analog.com> References: <20250403-togreg-v3-0-d4b06a4af5a9@analog.com> <20250403-togreg-v3-2-d4b06a4af5a9@analog.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.0 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Hi Kim, On Thu, 2025-04-03 at 13:33 +0800, Kim Seer Paller wrote: > Document the AD3530/AD3530R (8-channel) and AD3531/AD3531R (4-channel) > low-power, 16-bit, buffered voltage output DACs with software- > programmable gain controls. They provide full-scale output spans of 2.5V > or 5V for reference voltages of 2.5V. These devices operate on a single > 2.7V to 5.5V supply and are guaranteed to be monotonic by design. > The "R" variants include a 2.5V, 5ppm/=C2=B0C internal reference, which i= s > disabled by default. >=20 > Signed-off-by: Kim Seer Paller > --- > =C2=A0.../devicetree/bindings/iio/dac/adi,ad3530r.yaml=C2=A0=C2=A0 | 99 > ++++++++++++++++++++++ > =C2=A0MAINTAINERS=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 7 ++ > =C2=A02 files changed, 106 insertions(+) >=20 > diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad3530r.yaml > b/Documentation/devicetree/bindings/iio/dac/adi,ad3530r.yaml > new file mode 100644 > index > 0000000000000000000000000000000000000000..cf4a3eb98f1fa30afdeb0740bba7f05= 2d8ec > 2cd4 > --- /dev/null > +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad3530r.yaml > @@ -0,0 +1,99 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/iio/dac/adi,ad3530r.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Analog Devices AD3530R and Similar DACs > + > +maintainers: > +=C2=A0 - Kim Seer Paller > + > +description: | > +=C2=A0 The AD3530/AD3530R (8-channel) and AD3531/AD3531R (4-channel) are= low- > power, > +=C2=A0 16-bit, buffered voltage output digital-to-analog converters (DAC= s) with > +=C2=A0 software-programmable gain controls, providing full-scale output = spans of > 2.5V > +=C2=A0 or 5V for reference voltages of 2.5V. These devices operate from = a single > 2.7V > +=C2=A0 to 5.5V supply and are guaranteed monotonic by design. The "R" va= riants > +=C2=A0 include a 2.5V, 5ppm/=C2=B0C internal reference, which is disable= d by default. > +=C2=A0 Datasheet can be found here: > +=C2=A0 > https://www.analog.com/media/en/technical-documentation/data-sheets/ad353= 0_ad530r.pdf > + > +properties: > +=C2=A0 compatible: > +=C2=A0=C2=A0=C2=A0 enum: > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - adi,ad3530 > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - adi,ad3530r > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - adi,ad3531 > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - adi,ad3531r > + > +=C2=A0 reg: > +=C2=A0=C2=A0=C2=A0 maxItems: 1 > + > +=C2=A0 spi-max-frequency: > +=C2=A0=C2=A0=C2=A0 maximum: 50000000 > + > +=C2=A0 vdd-supply: > +=C2=A0=C2=A0=C2=A0 description: Power Supply Input. > + > +=C2=A0 iovdd-supply: > +=C2=A0=C2=A0=C2=A0 description: Digital Power Supply Input. > + > +=C2=A0 io-channels: > +=C2=A0=C2=A0=C2=A0 description: > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ADC channel used to monitor internal die = temperature, output voltages, > and > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 current of a selected channel via the MUX= OUT pin. > +=C2=A0=C2=A0=C2=A0 maxItems: 1 >=20 I'm a bit puzzled... Isn't this device the provider of such a channel? Therefore, I believe we should have #io-channel-cells, right? - Nuno S=C3=A1