[PATCH v5 0/5] Add peripherals for J784S4

[PATCH v5 0/5] Add peripherals for J784S4

[Jayesh Choudhary]

This series adds support for:
- SERDES, WIZ DT nodes, Serdes lane control mux
- MAIN CPSW2G nodes
- DSS and DisplayPort-0 nodes

Changelog v4->v5:
- rebased the patches on linux-next tip.

Changelog v3->v4:
- add reg property to serdes_ln_ctrl and fix the node name again to
  get rid of dtbs_check error.
- reorder reg, reg-names and ranges property for main_cpsw1.
- correct the order for clocks in serdes_wiz nodes to fix dtbs_check
  warnings.
- fix indentation in reg, reg-names and clock property for dss node.
- add comments for the reg type in dss registers.

Changelog v3->v2:
- fix dtc warnings for 'scm_conf' and 'serdes_ln_ctrl' nodes
  (Checked all the changes of the series with W=12 option during build)
- added clock-frequency for serdes_refclk along with other EVM changes
  This refclk is being used by all the instances of serdes_wiz which
  are disabled by default. So configuring refclk when the serdes nodes
  are used for the first time is okay.

Changelog v1->v2:
- Moved J784S4 EVM changes together to the last patch
  (Suggested by Andrew)

v4 patch link:
<https://lore.kernel.org/all/20230425131607.290707-1-j-choudhary@ti.com/>

Rahul T R (2):
  arm64: dts: ti: k3-j784s4-main: Add DSS and DP-bridge node
  arm64: dts: ti: k3-j784s4-evm: Enable DisplayPort-0

Siddharth Vadapalli (3):
  arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane
    mux
  arm64: dts: ti: k3-j784s4: Add Main CPSW2G node
  arm64: dts: ti: k3-j784s4: Add WIZ and SERDES PHY nodes

 arch/arm64/boot/dts/ti/k3-j784s4-evm.dts   | 164 ++++++++++
 arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 335 +++++++++++++++++++++
 2 files changed, 499 insertions(+)

-- 
2.25.1

[PATCH v5 1/5] arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane mux

[Jayesh Choudhary]

From: Siddharth Vadapalli <s-vadapalli@ti.com>

The system controller node manages the CTRL_MMR0 region.
Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
[j-choudhary@ti.com: Add reg property to fix dtc warning]
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index 2ea0adae6832..68cc2fa053e7 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -5,6 +5,9 @@
  * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
  */
 
+#include <dt-bindings/mux/mux.h>
+#include <dt-bindings/mux/ti-serdes.h>
+
 &cbass_main {
 	msmc_ram: sram@70000000 {
 		compatible = "mmio-sram";
@@ -26,6 +29,26 @@ l3cache-sram@200000 {
 		};
 	};
 
+	scm_conf: syscon@100000 {
+		compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
+		reg = <0x00 0x00100000 0x00 0x1c000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x00 0x00 0x00100000 0x1c000>;
+
+		serdes_ln_ctrl: mux-controller@4080 {
+			compatible = "mmio-mux";
+			reg = <0x00004080 0x30>;
+			#mux-control-cells = <1>;
+			mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
+					<0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */
+					<0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
+					<0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */
+					<0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
+					<0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */
+		};
+	};
+
 	gic500: interrupt-controller@1800000 {
 		compatible = "arm,gic-v3";
 		#address-cells = <2>;
-- 
2.25.1

Re: [PATCH v5 1/5] arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane mux

[Krzysztof Kozlowski]

On 10/07/2023 12:17, Jayesh Choudhary wrote:
> From: Siddharth Vadapalli <s-vadapalli@ti.com>
> 
> The system controller node manages the CTRL_MMR0 region.
> Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux.
> 
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> [j-choudhary@ti.com: Add reg property to fix dtc warning]
> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 23 ++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> index 2ea0adae6832..68cc2fa053e7 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> @@ -5,6 +5,9 @@
>   * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
>   */
>  
> +#include <dt-bindings/mux/mux.h>
> +#include <dt-bindings/mux/ti-serdes.h>

Why? What do you use from that binding?

Best regards,
Krzysztof

Re: [PATCH v5 1/5] arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane mux

[Jayesh Choudhary]

On 10/07/23 17:13, Krzysztof Kozlowski wrote:
> On 10/07/2023 12:17, Jayesh Choudhary wrote:
>> From: Siddharth Vadapalli <s-vadapalli@ti.com>
>>
>> The system controller node manages the CTRL_MMR0 region.
>> Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux.
>>
>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
>> [j-choudhary@ti.com: Add reg property to fix dtc warning]
>> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
>> ---
>>   arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 23 ++++++++++++++++++++++
>>   1 file changed, 23 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
>> index 2ea0adae6832..68cc2fa053e7 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
>> @@ -5,6 +5,9 @@
>>    * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
>>    */
>>   
>> +#include <dt-bindings/mux/mux.h>
>> +#include <dt-bindings/mux/ti-serdes.h>
> 
> Why? What do you use from that binding?
> 

Missed idle-state in the mux-controller node here for default values.
I will wait for more feedback and then re-spin the series.

Thanks,
-Jayesh

Re: [PATCH v5 1/5] arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane mux

[Nishanth Menon]

On 12:01-20230711, Jayesh Choudhary wrote:
> 
> 
> On 10/07/23 17:13, Krzysztof Kozlowski wrote:
> > On 10/07/2023 12:17, Jayesh Choudhary wrote:
> > > From: Siddharth Vadapalli <s-vadapalli@ti.com>
> > > 
> > > The system controller node manages the CTRL_MMR0 region.
> > > Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux.
> > > 
> > > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> > > [j-choudhary@ti.com: Add reg property to fix dtc warning]
> > > Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
> > > ---
> > >   arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 23 ++++++++++++++++++++++
> > >   1 file changed, 23 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> > > index 2ea0adae6832..68cc2fa053e7 100644
> > > --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> > > +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> > > @@ -5,6 +5,9 @@
> > >    * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
> > >    */
> > > +#include <dt-bindings/mux/mux.h>
> > > +#include <dt-bindings/mux/ti-serdes.h>
> > 
> > Why? What do you use from that binding?
> > 
> 
> Missed idle-state in the mux-controller node here for default values.
> I will wait for more feedback and then re-spin the series.

btw, I am wondering if ti-serdes.h should even exist in dt-bindings -
are any of the macros used in the driver? or should this follow the
pinctrl style macros that could happily reside in arch/arm64/boot/dts/ti
?


-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH v5 1/5] arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane mux

[Krzysztof Kozlowski]

On 11/07/2023 17:31, Nishanth Menon wrote:
> On 12:01-20230711, Jayesh Choudhary wrote:
>>
>>
>> On 10/07/23 17:13, Krzysztof Kozlowski wrote:
>>> On 10/07/2023 12:17, Jayesh Choudhary wrote:
>>>> From: Siddharth Vadapalli <s-vadapalli@ti.com>
>>>>
>>>> The system controller node manages the CTRL_MMR0 region.
>>>> Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux.
>>>>
>>>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
>>>> [j-choudhary@ti.com: Add reg property to fix dtc warning]
>>>> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
>>>> ---
>>>>   arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 23 ++++++++++++++++++++++
>>>>   1 file changed, 23 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
>>>> index 2ea0adae6832..68cc2fa053e7 100644
>>>> --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
>>>> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
>>>> @@ -5,6 +5,9 @@
>>>>    * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
>>>>    */
>>>> +#include <dt-bindings/mux/mux.h>
>>>> +#include <dt-bindings/mux/ti-serdes.h>
>>>
>>> Why? What do you use from that binding?
>>>
>>
>> Missed idle-state in the mux-controller node here for default values.
>> I will wait for more feedback and then re-spin the series.
> 
> btw, I am wondering if ti-serdes.h should even exist in dt-bindings -
> are any of the macros used in the driver? or should this follow the
> pinctrl style macros that could happily reside in arch/arm64/boot/dts/ti
> ?

I don't see any usage in drivers, which is a clear indication that it
might not be suitable for bindings. What are these values? Look like
some register values, which there is little sense in making a binding.

Best regards,
Krzysztof

Re: [PATCH v5 1/5] arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane mux

[Roger Quadros]

On 12/07/2023 08:44, Krzysztof Kozlowski wrote:
> On 11/07/2023 17:31, Nishanth Menon wrote:
>> On 12:01-20230711, Jayesh Choudhary wrote:
>>>
>>>
>>> On 10/07/23 17:13, Krzysztof Kozlowski wrote:
>>>> On 10/07/2023 12:17, Jayesh Choudhary wrote:
>>>>> From: Siddharth Vadapalli <s-vadapalli@ti.com>
>>>>>
>>>>> The system controller node manages the CTRL_MMR0 region.
>>>>> Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux.
>>>>>
>>>>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
>>>>> [j-choudhary@ti.com: Add reg property to fix dtc warning]
>>>>> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
>>>>> ---
>>>>>   arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 23 ++++++++++++++++++++++
>>>>>   1 file changed, 23 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
>>>>> index 2ea0adae6832..68cc2fa053e7 100644
>>>>> --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
>>>>> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
>>>>> @@ -5,6 +5,9 @@
>>>>>    * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
>>>>>    */
>>>>> +#include <dt-bindings/mux/mux.h>
>>>>> +#include <dt-bindings/mux/ti-serdes.h>
>>>>
>>>> Why? What do you use from that binding?
>>>>
>>>
>>> Missed idle-state in the mux-controller node here for default values.
>>> I will wait for more feedback and then re-spin the series.
>>
>> btw, I am wondering if ti-serdes.h should even exist in dt-bindings -
>> are any of the macros used in the driver? or should this follow the
>> pinctrl style macros that could happily reside in arch/arm64/boot/dts/ti
>> ?
> 
> I don't see any usage in drivers, which is a clear indication that it
> might not be suitable for bindings. What are these values? Look like
> some register values, which there is little sense in making a binding.
> 
> Best regards,
> Krzysztof
> 
> 

You are right. They are constants not used in the driver directly.
mmio-mux driver uses it to set the idle state of the mux via the
'idle-states' property.

I agree with Nishanth that they should be moved to arch/arm64/boot/dts/ti

-- 
cheers,
-roger

Re: [PATCH v5 1/5] arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane mux

[Jayesh Choudhary]

On 12/07/23 16:51, Roger Quadros wrote:
> 
> 
> On 12/07/2023 08:44, Krzysztof Kozlowski wrote:
>> On 11/07/2023 17:31, Nishanth Menon wrote:
>>> On 12:01-20230711, Jayesh Choudhary wrote:
>>>>
>>>>
>>>> On 10/07/23 17:13, Krzysztof Kozlowski wrote:
>>>>> On 10/07/2023 12:17, Jayesh Choudhary wrote:
>>>>>> From: Siddharth Vadapalli <s-vadapalli@ti.com>
>>>>>>
>>>>>> The system controller node manages the CTRL_MMR0 region.
>>>>>> Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux.
>>>>>>
>>>>>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
>>>>>> [j-choudhary@ti.com: Add reg property to fix dtc warning]
>>>>>> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
>>>>>> ---
>>>>>>    arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 23 ++++++++++++++++++++++
>>>>>>    1 file changed, 23 insertions(+)
>>>>>>
>>>>>> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
>>>>>> index 2ea0adae6832..68cc2fa053e7 100644
>>>>>> --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
>>>>>> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
>>>>>> @@ -5,6 +5,9 @@
>>>>>>     * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
>>>>>>     */
>>>>>> +#include <dt-bindings/mux/mux.h>
>>>>>> +#include <dt-bindings/mux/ti-serdes.h>
>>>>>
>>>>> Why? What do you use from that binding?
>>>>>
>>>>
>>>> Missed idle-state in the mux-controller node here for default values.
>>>> I will wait for more feedback and then re-spin the series.
>>>
>>> btw, I am wondering if ti-serdes.h should even exist in dt-bindings -
>>> are any of the macros used in the driver? or should this follow the
>>> pinctrl style macros that could happily reside in arch/arm64/boot/dts/ti
>>> ?
>>
>> I don't see any usage in drivers, which is a clear indication that it
>> might not be suitable for bindings. What are these values? Look like
>> some register values, which there is little sense in making a binding.
>>
>> Best regards,
>> Krzysztof
>>
>>
> 
> You are right. They are constants not used in the driver directly.
> mmio-mux driver uses it to set the idle state of the mux via the
> 'idle-states' property.
> 
> I agree with Nishanth that they should be moved to arch/arm64/boot/dts/ti
> 

Then I will do the cleanup for all platforms and then post the dependent
series before spinning v6.

Thanks and Warm regards,
-Jayesh

[PATCH v5 2/5] arm64: dts: ti: k3-j784s4: Add Main CPSW2G node

[Jayesh Choudhary]

From: Siddharth Vadapalli <s-vadapalli@ti.com>

J784S4 SoC has a Main CPSW2G instance of the CPSW Ethernet Switch.

Add the device-tree nodes for the Main CPSW2G instance and enable it.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
[j-choudhary@ti.com: minor cleanups]
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j784s4-evm.dts   | 48 +++++++++++++++
 arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 68 ++++++++++++++++++++++
 2 files changed, 116 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index 430b8a2c5df5..32a3c88cdda5 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -252,6 +252,30 @@ vdd_sd_dv: regulator-TLV71033 {
 };
 
 &main_pmx0 {
+	main_cpsw2g_pins_default: main-cpsw2g-pins-default {
+		pinctrl-single,pins = <
+			J784S4_IOPAD(0x0b8, PIN_INPUT, 6) /* (AC34) MCASP1_ACLKX.RGMII1_RD0 */
+			J784S4_IOPAD(0x0a0, PIN_INPUT, 6) /* (AD34) MCASP0_AXR12.RGMII1_RD1 */
+			J784S4_IOPAD(0x0a4, PIN_INPUT, 6) /* (AJ36) MCASP0_AXR13.RGMII1_RD2 */
+			J784S4_IOPAD(0x0a8, PIN_INPUT, 6) /* (AF34) MCASP0_AXR14.RGMII1_RD3 */
+			J784S4_IOPAD(0x0b0, PIN_INPUT, 6) /* (AL33) MCASP1_AXR3.RGMII1_RXC */
+			J784S4_IOPAD(0x0ac, PIN_INPUT, 6) /* (AE34) MCASP0_AXR15.RGMII1_RX_CTL */
+			J784S4_IOPAD(0x08c, PIN_INPUT, 6) /* (AE35) MCASP0_AXR7.RGMII1_TD0 */
+			J784S4_IOPAD(0x090, PIN_INPUT, 6) /* (AC35) MCASP0_AXR8.RGMII1_TD1 */
+			J784S4_IOPAD(0x094, PIN_INPUT, 6) /* (AG35) MCASP0_AXR9.RGMII1_TD2 */
+			J784S4_IOPAD(0x098, PIN_INPUT, 6) /* (AH36) MCASP0_AXR10.RGMII1_TD3 */
+			J784S4_IOPAD(0x0b4, PIN_INPUT, 6) /* (AL34) MCASP1_AXR4.RGMII1_TXC */
+			J784S4_IOPAD(0x09c, PIN_INPUT, 6) /* (AF35) MCASP0_AXR11.RGMII1_TX_CTL */
+		>;
+	};
+
+	main_cpsw2g_mdio_pins_default: main-cpsw2g-mdio-pins-default {
+		pinctrl-single,pins = <
+			J784S4_IOPAD(0x0c0, PIN_INPUT, 6) /* (AD38) MCASP1_AXR0.MDIO0_MDC */
+			J784S4_IOPAD(0x0bc, PIN_INPUT, 6) /* (AD33) MCASP1_AFSX.MDIO0_MDIO */
+		>;
+	};
+
 	main_uart8_pins_default: main-uart8-default-pins {
 		pinctrl-single,pins = <
 			J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */
@@ -827,3 +851,27 @@ adc {
 		ti,adc-channels = <0 1 2 3 4 5 6 7>;
 	};
 };
+
+&main_cpsw1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_cpsw2g_pins_default>;
+};
+
+&main_cpsw1_mdio {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_cpsw2g_mdio_pins_default>;
+
+	main_phy0: ethernet-phy@0 {
+		reg = <0>;
+		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+		ti,min-output-impedance;
+	};
+};
+
+&main_cpsw1_port1 {
+	status = "okay";
+	phy-mode = "rgmii-rxid";
+	phy-handle = <&main_phy0>;
+};
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index 68cc2fa053e7..baffa8428d64 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -36,6 +36,12 @@ scm_conf: syscon@100000 {
 		#size-cells = <1>;
 		ranges = <0x00 0x00 0x00100000 0x1c000>;
 
+		cpsw1_phy_gmii_sel: phy@4034 {
+			compatible = "ti,am654-phy-gmii-sel";
+			reg = <0x4034 0x4>;
+			#phy-cells = <1>;
+		};
+
 		serdes_ln_ctrl: mux-controller@4080 {
 			compatible = "mmio-mux";
 			reg = <0x00004080 0x30>;
@@ -1035,6 +1041,68 @@ cpts@310d0000 {
 		};
 	};
 
+	main_cpsw1: ethernet@c200000 {
+		compatible = "ti,j721e-cpsw-nuss";
+		reg = <0x00 0xc200000 0x00 0x200000>;
+		reg-names = "cpsw_nuss";
+		ranges = <0x00 0x00 0x00 0xc200000 0x00 0x200000>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		dma-coherent;
+		clocks = <&k3_clks 62 0>;
+		clock-names = "fck";
+		power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
+
+		dmas = <&main_udmap 0xc640>,
+		       <&main_udmap 0xc641>,
+		       <&main_udmap 0xc642>,
+		       <&main_udmap 0xc643>,
+		       <&main_udmap 0xc644>,
+		       <&main_udmap 0xc645>,
+		       <&main_udmap 0xc646>,
+		       <&main_udmap 0xc647>,
+		       <&main_udmap 0x4640>;
+		dma-names = "tx0", "tx1", "tx2", "tx3",
+			    "tx4", "tx5", "tx6", "tx7",
+			    "rx";
+
+		status = "disabled";
+
+		ethernet-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			main_cpsw1_port1: port@1 {
+				reg = <1>;
+				label = "port1";
+				phys = <&cpsw1_phy_gmii_sel 1>;
+				ti,mac-only;
+				status = "disabled";
+			};
+		};
+
+		main_cpsw1_mdio: mdio@f00 {
+			compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
+			reg = <0x00 0xf00 0x00 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&k3_clks 62 0>;
+			clock-names = "fck";
+			bus_freq = <1000000>;
+		};
+
+		cpts@3d000 {
+			compatible = "ti,am65-cpts";
+			reg = <0x00 0x3d000 0x00 0x400>;
+			clocks = <&k3_clks 62 3>;
+			clock-names = "cpts";
+			interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "cpts";
+			ti,cpts-ext-ts-inputs = <4>;
+			ti,cpts-periodic-outputs = <2>;
+		};
+	};
+
 	main_mcan0: can@2701000 {
 		compatible = "bosch,m_can";
 		reg = <0x00 0x02701000 0x00 0x200>,
-- 
2.25.1

[PATCH v5 3/5] arm64: dts: ti: k3-j784s4: Add WIZ and SERDES PHY nodes

[Jayesh Choudhary]

From: Siddharth Vadapalli <s-vadapalli@ti.com>

J784S4 SoC has 4 Serdes instances along with their respective WIZ
instances. Add device-tree nodes for them and disable them by default.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
[j-choudhary@ti.com: fix serdes_wiz clock order]
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 171 +++++++++++++++++++++
 1 file changed, 171 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index baffa8428d64..151921f73848 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -7,6 +7,15 @@
 
 #include <dt-bindings/mux/mux.h>
 #include <dt-bindings/mux/ti-serdes.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/phy/phy-ti.h>
+
+/ {
+	serdes_refclk: serdes-refclk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+	};
+};
 
 &cbass_main {
 	msmc_ram: sram@70000000 {
@@ -698,6 +707,168 @@ main_sdhci1: mmc@4fb0000 {
 		status = "disabled";
 	};
 
+	serdes_wiz0: wiz@5060000 {
+		compatible = "ti,j784s4-wiz-10g";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		power-domains = <&k3_pds 404 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 404 2>, <&k3_clks 404 6>, <&serdes_refclk>, <&k3_clks 404 5>;
+		clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
+		assigned-clocks = <&k3_clks 404 6>;
+		assigned-clock-parents = <&k3_clks 404 10>;
+		num-lanes = <4>;
+		#reset-cells = <1>;
+		#clock-cells = <1>;
+		ranges = <0x5060000 0x00 0x5060000 0x10000>;
+
+		status = "disabled";
+
+		serdes0: serdes@5060000 {
+			compatible = "ti,j721e-serdes-10g";
+			reg = <0x05060000 0x010000>;
+			reg-names = "torrent_phy";
+			resets = <&serdes_wiz0 0>;
+			reset-names = "torrent_reset";
+			clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+				 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
+			clock-names = "refclk", "phy_en_refclk";
+			assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+					  <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
+					  <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
+			assigned-clock-parents = <&k3_clks 404 6>,
+						 <&k3_clks 404 6>,
+						 <&k3_clks 404 6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#clock-cells = <1>;
+
+			status = "disabled";
+		};
+	};
+
+	serdes_wiz1: wiz@5070000 {
+		compatible = "ti,j784s4-wiz-10g";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		power-domains = <&k3_pds 405 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 405 2>, <&k3_clks 405 6>, <&serdes_refclk>, <&k3_clks 405 5>;
+		clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
+		assigned-clocks = <&k3_clks 405 6>;
+		assigned-clock-parents = <&k3_clks 405 10>;
+		num-lanes = <4>;
+		#reset-cells = <1>;
+		#clock-cells = <1>;
+		ranges = <0x05070000 0x00 0x05070000 0x10000>;
+
+		status = "disabled";
+
+		serdes1: serdes@5070000 {
+			compatible = "ti,j721e-serdes-10g";
+			reg = <0x05070000 0x010000>;
+			reg-names = "torrent_phy";
+			resets = <&serdes_wiz1 0>;
+			reset-names = "torrent_reset";
+			clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
+				 <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>;
+			clock-names = "refclk", "phy_en_refclk";
+			assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
+					  <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>,
+					  <&serdes_wiz1 TI_WIZ_REFCLK_DIG>;
+			assigned-clock-parents = <&k3_clks 405 6>,
+						 <&k3_clks 405 6>,
+						 <&k3_clks 405 6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#clock-cells = <1>;
+
+			status = "disabled";
+		};
+	};
+
+	serdes_wiz2: wiz@5020000 {
+		compatible = "ti,j784s4-wiz-10g";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		power-domains = <&k3_pds 406 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 406 2>, <&k3_clks 406 6>, <&serdes_refclk>, <&k3_clks 406 5>;
+		clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
+		assigned-clocks = <&k3_clks 406 6>;
+		assigned-clock-parents = <&k3_clks 406 10>;
+		num-lanes = <4>;
+		#reset-cells = <1>;
+		#clock-cells = <1>;
+		ranges = <0x05020000 0x00 0x05020000 0x10000>;
+
+		status = "disabled";
+
+		serdes2: serdes@5020000 {
+			compatible = "ti,j721e-serdes-10g";
+			reg = <0x05020000 0x010000>;
+			reg-names = "torrent_phy";
+			resets = <&serdes_wiz2 0>;
+			reset-names = "torrent_reset";
+			clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
+				 <&serdes_wiz2 TI_WIZ_PHY_EN_REFCLK>;
+			clock-names = "refclk", "phy_en_refclk";
+			assigned-clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
+					  <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>,
+					  <&serdes_wiz2 TI_WIZ_REFCLK_DIG>;
+			assigned-clock-parents = <&k3_clks 406 6>,
+						 <&k3_clks 406 6>,
+						 <&k3_clks 406 6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#clock-cells = <1>;
+
+			status = "disabled";
+		};
+	};
+
+	serdes_wiz4: wiz@5050000 {
+		compatible = "ti,j784s4-wiz-10g";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		power-domains = <&k3_pds 407 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 407 2>, <&k3_clks 407 6>, <&serdes_refclk>, <&k3_clks 407 5>;
+		clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
+		assigned-clocks = <&k3_clks 407 6>;
+		assigned-clock-parents = <&k3_clks 407 10>;
+		num-lanes = <4>;
+		#reset-cells = <1>;
+		#clock-cells = <1>;
+		ranges = <0x05050000 0x00 0x05050000 0x10000>,
+			 <0xa030a00 0x00 0xa030a00 0x40>; /* DPTX PHY */
+
+		status = "disabled";
+
+		serdes4: serdes@5050000 {
+			/*
+			 * Note: we also map DPTX PHY registers as the Torrent
+			 * needs to manage those.
+			 */
+			compatible = "ti,j721e-serdes-10g";
+			reg = <0x05050000 0x010000>,
+			      <0x0a030a00 0x40>; /* DPTX PHY */
+			reg-names = "torrent_phy";
+			resets = <&serdes_wiz4 0>;
+			reset-names = "torrent_reset";
+			clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
+				 <&serdes_wiz4 TI_WIZ_PHY_EN_REFCLK>;
+			clock-names = "refclk", "phy_en_refclk";
+			assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
+					  <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>,
+					  <&serdes_wiz4 TI_WIZ_REFCLK_DIG>;
+			assigned-clock-parents = <&k3_clks 407 6>,
+						 <&k3_clks 407 6>,
+						 <&k3_clks 407 6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#clock-cells = <1>;
+
+			status = "disabled";
+		};
+	};
+
 	main_navss: bus@30000000 {
 		compatible = "simple-bus";
 		#address-cells = <2>;
-- 
2.25.1

Re: [PATCH v5 3/5] arm64: dts: ti: k3-j784s4: Add WIZ and SERDES PHY nodes

[Nishanth Menon]

On 15:47-20230710, Jayesh Choudhary wrote:
> From: Siddharth Vadapalli <s-vadapalli@ti.com>
> 
> J784S4 SoC has 4 Serdes instances along with their respective WIZ
> instances. Add device-tree nodes for them and disable them by default.
> 
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> [j-choudhary@ti.com: fix serdes_wiz clock order]
> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
> ---
NAK. This patch introduces the following dtbs_check warning.
arch/arm64/boot/dts/ti/k3-am69-sk.dtb: serdes-refclk: 'clock-frequency' is a required property

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH v5 3/5] arm64: dts: ti: k3-j784s4: Add WIZ and SERDES PHY nodes

[Jayesh Choudhary]

On 12/07/23 19:48, Nishanth Menon wrote:
> On 15:47-20230710, Jayesh Choudhary wrote:
>> From: Siddharth Vadapalli <s-vadapalli@ti.com>
>>
>> J784S4 SoC has 4 Serdes instances along with their respective WIZ
>> instances. Add device-tree nodes for them and disable them by default.
>>
>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
>> [j-choudhary@ti.com: fix serdes_wiz clock order]
>> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
>> ---
> NAK. This patch introduces the following dtbs_check warning.
> arch/arm64/boot/dts/ti/k3-am69-sk.dtb: serdes-refclk: 'clock-frequency' is a required property
> 

Sorry for this. This property was added in the final board file.
I will fix it in the next revision.
I will add '0' as clock-property in the main file similar to j721e[1]
which will be overridden in the board file with required value to get
rid of this warning.

Warm Regards,
-Jayesh

[1]: 
<https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi#n16>

Re: [PATCH v5 3/5] arm64: dts: ti: k3-j784s4: Add WIZ and SERDES PHY nodes

[Nishanth Menon]

On 21:01-20230713, Jayesh Choudhary wrote:
> 
> 
> On 12/07/23 19:48, Nishanth Menon wrote:
> > On 15:47-20230710, Jayesh Choudhary wrote:
> > > From: Siddharth Vadapalli <s-vadapalli@ti.com>
> > > 
> > > J784S4 SoC has 4 Serdes instances along with their respective WIZ
> > > instances. Add device-tree nodes for them and disable them by default.
> > > 
> > > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> > > [j-choudhary@ti.com: fix serdes_wiz clock order]
> > > Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
> > > ---
> > NAK. This patch introduces the following dtbs_check warning.
> > arch/arm64/boot/dts/ti/k3-am69-sk.dtb: serdes-refclk: 'clock-frequency' is a required property
> > 
> 
> Sorry for this. This property was added in the final board file.
> I will fix it in the next revision.
> I will add '0' as clock-property in the main file similar to j721e[1]
> which will be overridden in the board file with required value to get
> rid of this warning.

That would follow what renesas (r8a774a1.dtsi) and imx
(imx8dxl-ss-conn.dtsi) seem to be doing as well. Just make sure to add
documentation to the property to indicate expectation. Unless someone
has objections to this approach.

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH v5 3/5] arm64: dts: ti: k3-j784s4: Add WIZ and SERDES PHY nodes

[Andrew Davis]

On 7/13/23 1:21 PM, Nishanth Menon wrote:
> On 21:01-20230713, Jayesh Choudhary wrote:
>>
>>
>> On 12/07/23 19:48, Nishanth Menon wrote:
>>> On 15:47-20230710, Jayesh Choudhary wrote:
>>>> From: Siddharth Vadapalli <s-vadapalli@ti.com>
>>>>
>>>> J784S4 SoC has 4 Serdes instances along with their respective WIZ
>>>> instances. Add device-tree nodes for them and disable them by default.
>>>>
>>>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
>>>> [j-choudhary@ti.com: fix serdes_wiz clock order]
>>>> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
>>>> ---
>>> NAK. This patch introduces the following dtbs_check warning.
>>> arch/arm64/boot/dts/ti/k3-am69-sk.dtb: serdes-refclk: 'clock-frequency' is a required property
>>>
>>
>> Sorry for this. This property was added in the final board file.
>> I will fix it in the next revision.
>> I will add '0' as clock-property in the main file similar to j721e[1]
>> which will be overridden in the board file with required value to get
>> rid of this warning.
> 
> That would follow what renesas (r8a774a1.dtsi) and imx
> (imx8dxl-ss-conn.dtsi) seem to be doing as well. Just make sure to add
> documentation to the property to indicate expectation. Unless someone
> has objections to this approach.
> 

Would it work better to disable these nodes, only enabling them in the
board files when a real clock-frequency can be provided?

My initial reaction would be to move the whole external reference clock
node to the board file since that is where it is provided, but seems
that would cause more churn in serdes_wiz* nodes than we would want..

Andrew

Re: [PATCH v5 3/5] arm64: dts: ti: k3-j784s4: Add WIZ and SERDES PHY nodes

[Nishanth Menon]

On 13:31-20230713, Andrew Davis wrote:
> On 7/13/23 1:21 PM, Nishanth Menon wrote:
> > On 21:01-20230713, Jayesh Choudhary wrote:
> > > 
> > > 
> > > On 12/07/23 19:48, Nishanth Menon wrote:
> > > > On 15:47-20230710, Jayesh Choudhary wrote:
> > > > > From: Siddharth Vadapalli <s-vadapalli@ti.com>
> > > > > 
> > > > > J784S4 SoC has 4 Serdes instances along with their respective WIZ
> > > > > instances. Add device-tree nodes for them and disable them by default.
> > > > > 
> > > > > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> > > > > [j-choudhary@ti.com: fix serdes_wiz clock order]
> > > > > Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
> > > > > ---
> > > > NAK. This patch introduces the following dtbs_check warning.
> > > > arch/arm64/boot/dts/ti/k3-am69-sk.dtb: serdes-refclk: 'clock-frequency' is a required property
> > > > 
> > > 
> > > Sorry for this. This property was added in the final board file.
> > > I will fix it in the next revision.
> > > I will add '0' as clock-property in the main file similar to j721e[1]
> > > which will be overridden in the board file with required value to get
> > > rid of this warning.
> > 
> > That would follow what renesas (r8a774a1.dtsi) and imx
> > (imx8dxl-ss-conn.dtsi) seem to be doing as well. Just make sure to add
> > documentation to the property to indicate expectation. Unless someone
> > has objections to this approach.
> > 
> 
> Would it work better to disable these nodes, only enabling them in the
> board files when a real clock-frequency can be provided?
> 
> My initial reaction would be to move the whole external reference clock
> node to the board file since that is where it is provided, but seems
> that would cause more churn in serdes_wiz* nodes than we would want..

I would prefer that as well, but I have'nt gone around looking for
similar examples on other SoCs (Jayesh, can you check?). One other
approach (alipine and few other places) has been for the bootloader to
update the property set in dtb as 0, which is not needed in this case
to the best of what I see.. just hoping we use a technique that most
board folks are familiar with across SoCs.

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH v5 3/5] arm64: dts: ti: k3-j784s4: Add WIZ and SERDES PHY nodes

[Jayesh Choudhary]

On 14/07/23 00:28, Nishanth Menon wrote:
> On 13:31-20230713, Andrew Davis wrote:
>> On 7/13/23 1:21 PM, Nishanth Menon wrote:
>>> On 21:01-20230713, Jayesh Choudhary wrote:
>>>>
>>>>
>>>> On 12/07/23 19:48, Nishanth Menon wrote:
>>>>> On 15:47-20230710, Jayesh Choudhary wrote:
>>>>>> From: Siddharth Vadapalli <s-vadapalli@ti.com>
>>>>>>
>>>>>> J784S4 SoC has 4 Serdes instances along with their respective WIZ
>>>>>> instances. Add device-tree nodes for them and disable them by default.
>>>>>>
>>>>>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
>>>>>> [j-choudhary@ti.com: fix serdes_wiz clock order]
>>>>>> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
>>>>>> ---
>>>>> NAK. This patch introduces the following dtbs_check warning.
>>>>> arch/arm64/boot/dts/ti/k3-am69-sk.dtb: serdes-refclk: 'clock-frequency' is a required property
>>>>>
>>>>
>>>> Sorry for this. This property was added in the final board file.
>>>> I will fix it in the next revision.
>>>> I will add '0' as clock-property in the main file similar to j721e[1]
>>>> which will be overridden in the board file with required value to get
>>>> rid of this warning.
>>>
>>> That would follow what renesas (r8a774a1.dtsi) and imx
>>> (imx8dxl-ss-conn.dtsi) seem to be doing as well. Just make sure to add
>>> documentation to the property to indicate expectation. Unless someone
>>> has objections to this approach.
>>>
>>
>> Would it work better to disable these nodes, only enabling them in the
>> board files when a real clock-frequency can be provided?
>>
>> My initial reaction would be to move the whole external reference clock
>> node to the board file since that is where it is provided, but seems
>> that would cause more churn in serdes_wiz* nodes than we would want..
> 
> I would prefer that as well, but I have'nt gone around looking for
> similar examples on other SoCs (Jayesh, can you check?). One other
> approach (alipine and few other places) has been for the bootloader to
> update the property set in dtb as 0, which is not needed in this case
> to the best of what I see.. just hoping we use a technique that most
> board folks are familiar with across SoCs.
> 


I can see the clock nodes in board files for some vendors. But like
Andrew said, that would cause issues with serdes_wiz node in the
main.dtsi.

So I think it would be better to keep the external clock node in main
dtsi itself. I will add comments to the property to indicate that this
value will be over-written in board dts.
Posting v6 to address these comments and others on the series.

Thanks,
Jayesh

Re: [PATCH v5 3/5] arm64: dts: ti: k3-j784s4: Add WIZ and SERDES PHY nodes

[Jayesh Choudhary]

On 20/07/23 15:06, Jayesh Choudhary wrote:
> 
> 
> On 14/07/23 00:28, Nishanth Menon wrote:
>> On 13:31-20230713, Andrew Davis wrote:
>>> On 7/13/23 1:21 PM, Nishanth Menon wrote:
>>>> On 21:01-20230713, Jayesh Choudhary wrote:
>>>>>
>>>>>
>>>>> On 12/07/23 19:48, Nishanth Menon wrote:
>>>>>> On 15:47-20230710, Jayesh Choudhary wrote:
>>>>>>> From: Siddharth Vadapalli <s-vadapalli@ti.com>
>>>>>>>
>>>>>>> J784S4 SoC has 4 Serdes instances along with their respective WIZ
>>>>>>> instances. Add device-tree nodes for them and disable them by 
>>>>>>> default.
>>>>>>>
>>>>>>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
>>>>>>> [j-choudhary@ti.com: fix serdes_wiz clock order]
>>>>>>> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
>>>>>>> ---
>>>>>> NAK. This patch introduces the following dtbs_check warning.
>>>>>> arch/arm64/boot/dts/ti/k3-am69-sk.dtb: serdes-refclk: 
>>>>>> 'clock-frequency' is a required property
>>>>>>
>>>>>
>>>>> Sorry for this. This property was added in the final board file.
>>>>> I will fix it in the next revision.
>>>>> I will add '0' as clock-property in the main file similar to j721e[1]
>>>>> which will be overridden in the board file with required value to get
>>>>> rid of this warning.
>>>>
>>>> That would follow what renesas (r8a774a1.dtsi) and imx
>>>> (imx8dxl-ss-conn.dtsi) seem to be doing as well. Just make sure to add
>>>> documentation to the property to indicate expectation. Unless someone
>>>> has objections to this approach.
>>>>
>>>
>>> Would it work better to disable these nodes, only enabling them in the
>>> board files when a real clock-frequency can be provided?
>>>
>>> My initial reaction would be to move the whole external reference clock
>>> node to the board file since that is where it is provided, but seems
>>> that would cause more churn in serdes_wiz* nodes than we would want..
>>
>> I would prefer that as well, but I have'nt gone around looking for
>> similar examples on other SoCs (Jayesh, can you check?). One other
>> approach (alipine and few other places) has been for the bootloader to
>> update the property set in dtb as 0, which is not needed in this case
>> to the best of what I see.. just hoping we use a technique that most
>> board folks are familiar with across SoCs.
>>
> 
> 
> I can see the clock nodes in board files for some vendors. But like
> Andrew said, that would cause issues with serdes_wiz node in the
> main.dtsi.
> 
> So I think it would be better to keep the external clock node in main
> dtsi itself. I will add comments to the property to indicate that this
> value will be over-written in board dts.
> Posting v6 to address these comments and others on the series.
> 

FYI..
I posted v6: 
https://lore.kernel.org/all/20230721132029.123881-1-j-choudhary@ti.com/
And I am using status property instead to address the dtbs_warning here.

Warm Regards,
Jayesh

[PATCH v5 4/5] arm64: dts: ti: k3-j784s4-main: Add DSS and DP-bridge node

[Jayesh Choudhary]

From: Rahul T R <r-ravikumar@ti.com>

Add DSS and DP-bridge node for J784S4 SoC. DSS IP in J784S4 is
same as DSS IP in J721E, so same compatible is being used.
The DP is Cadence MHDP8546.

Signed-off-by: Rahul T R <r-ravikumar@ti.com>
[j-choudhary@ti.com: move dss & mhdp node together in main, fix dss node]
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 73 ++++++++++++++++++++++
 1 file changed, 73 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index 151921f73848..d6adab15e25e 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -1799,4 +1799,77 @@ c71_3: dsp@67800000 {
 		resets = <&k3_reset 40 1>;
 		firmware-name = "j784s4-c71_3-fw";
 	};
+
+	mhdp: dp-bridge@a000000 {
+		compatible = "ti,j721e-mhdp8546";
+
+		reg = <0x0 0xa000000 0x0 0x30a00>,
+		      <0x0 0x4f40000 0x0 0x20>;
+		reg-names = "mhdptx", "j721e-intg";
+
+		clocks = <&k3_clks 217 11>;
+
+		interrupt-parent = <&gic500>;
+		interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
+
+		power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
+
+		status = "disabled";
+
+		dp0_ports: ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+
+	dss: dss@4a00000 {
+		compatible = "ti,j721e-dss";
+		reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */
+		      <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
+		      <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
+		      <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
+		      <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
+		      <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
+		      <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
+		      <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
+		      <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
+		      <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
+		      <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
+		      <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
+		      <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
+		      <0x00 0x04aa0000 0x00 0x10000>, /* vp1 */
+		      <0x00 0x04ac0000 0x00 0x10000>, /* vp1 */
+		      <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
+		      <0x00 0x04af0000 0x00 0x10000>; /* wb */
+
+		reg-names = "common_m", "common_s0",
+			    "common_s1", "common_s2",
+			    "vidl1", "vidl2","vid1","vid2",
+			    "ovr1", "ovr2", "ovr3", "ovr4",
+			    "vp1", "vp2", "vp3", "vp4",
+			    "wb";
+
+		clocks = <&k3_clks 218 0>,
+			 <&k3_clks 218 2>,
+			 <&k3_clks 218 5>,
+			 <&k3_clks 218 14>,
+			 <&k3_clks 218 18>;
+		clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
+
+		power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
+
+		interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "common_m",
+				  "common_s0",
+				  "common_s1",
+				  "common_s2";
+
+		status = "disabled";
+
+		dss_ports: ports {
+		};
+	};
 };
-- 
2.25.1

[PATCH v5 5/5] arm64: dts: ti: k3-j784s4-evm: Enable DisplayPort-0

[Jayesh Choudhary]

From: Rahul T R <r-ravikumar@ti.com>

Enable display for J784S4 EVM.

Add assigned clocks for DSS, DT node for DisplayPort PHY and pinmux for
DP HPD. Add the clock frequency for serdes_refclk.

Add the endpoint nodes to describe connection from:
DSS => MHDP => DisplayPort connector.

Also add the GPIO expander-4 node and pinmux for main_i2c4 which is
required for controlling DP power. Set status for all required nodes
for DP-0 as "okay".

Signed-off-by: Rahul T R <r-ravikumar@ti.com>
[j-choudhary@ti.com: move all the changes together to enable DP-0 in EVM]
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 116 +++++++++++++++++++++++
 1 file changed, 116 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index 32a3c88cdda5..1678dfc5523b 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -249,6 +249,28 @@ vdd_sd_dv: regulator-TLV71033 {
 		states = <1800000 0x0>,
 			 <3300000 0x1>;
 	};
+
+	dp0_pwr_3v3: regulator-dp0-prw {
+		compatible = "regulator-fixed";
+		regulator-name = "dp0-pwr";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&exp4 0 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	dp0: dp0-connector {
+		compatible = "dp-connector";
+		label = "DP0";
+		type = "full-size";
+		dp-pwr-supply = <&dp0_pwr_3v3>;
+
+		port {
+			dp0_connector_in: endpoint {
+				remote-endpoint = <&dp0_out>;
+			};
+		};
+	};
 };
 
 &main_pmx0 {
@@ -310,6 +332,19 @@ vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
 			J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */
 		>;
 	};
+
+	dp0_pins_default: dp0-pins-default {
+		pinctrl-single,pins = <
+			J784S4_IOPAD(0x0cc, PIN_INPUT, 12) /* (AM37) SPI0_CS0.DP0_HPD */
+		>;
+	};
+
+	main_i2c4_pins_default: main-i2c4-pins-default {
+		pinctrl-single,pins = <
+			J784S4_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AG33) MCAN14_TX.I2C4_SCL */
+			J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */
+		>;
+	};
 };
 
 &wkup_pmx2 {
@@ -875,3 +910,84 @@ &main_cpsw1_port1 {
 	phy-mode = "rgmii-rxid";
 	phy-handle = <&main_phy0>;
 };
+
+&serdes_refclk {
+	clock-frequency = <100000000>;
+};
+
+&dss {
+	status = "okay";
+	assigned-clocks = <&k3_clks 218 2>,
+			  <&k3_clks 218 5>,
+			  <&k3_clks 218 14>,
+			  <&k3_clks 218 18>;
+	assigned-clock-parents = <&k3_clks 218 3>,
+				 <&k3_clks 218 7>,
+				 <&k3_clks 218 16>,
+				 <&k3_clks 218 22>;
+};
+
+&serdes_wiz4 {
+	status = "okay";
+};
+
+&serdes4 {
+	status = "okay";
+	serdes4_dp_link: phy@0 {
+		reg = <0>;
+		cdns,num-lanes = <4>;
+		#phy-cells = <0>;
+		cdns,phy-type = <PHY_TYPE_DP>;
+		resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>,
+			 <&serdes_wiz4 3>, <&serdes_wiz4 4>;
+	};
+};
+
+&mhdp {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&dp0_pins_default>;
+	phys = <&serdes4_dp_link>;
+	phy-names = "dpphy";
+};
+
+&dss_ports {
+	port {
+		dpi0_out: endpoint {
+			remote-endpoint = <&dp0_in>;
+		};
+	};
+};
+
+&main_i2c4 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_i2c4_pins_default>;
+	clock-frequency = <400000>;
+
+	exp4: gpio@20 {
+		compatible = "ti,tca6408";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
+
+&dp0_ports {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	port@0 {
+		reg = <0>;
+		dp0_in: endpoint {
+			remote-endpoint = <&dpi0_out>;
+		};
+	};
+
+	port@4 {
+		reg = <4>;
+		dp0_out: endpoint {
+			remote-endpoint = <&dp0_connector_in>;
+		};
+	};
+};
-- 
2.25.1