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[83.9.29.190]) by smtp.gmail.com with ESMTPSA id d2-20020ac25ec2000000b004f24e797c55sm2173418lfq.25.2023.06.14.08.26.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 14 Jun 2023 08:26:26 -0700 (PDT) Message-ID: Date: Wed, 14 Jun 2023 17:26:24 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.2 Subject: Re: [PATCH v4 1/2] arm64: dts: qcom: sc8280xp: Add GPU related nodes Content-Language: en-US To: Bjorn Andersson , Bjorn Andersson Cc: Rob Clark , Dmitry Baryshkov , Akhil P Oommen , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, freedreno@lists.freedesktop.org, johan@kernel.org, mani@kernel.org, Steev Klimaszewski , Johan Hovold References: <20230614142204.2675653-1-quic_bjorande@quicinc.com> <20230614142204.2675653-2-quic_bjorande@quicinc.com> From: Konrad Dybcio In-Reply-To: <20230614142204.2675653-2-quic_bjorande@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 14.06.2023 16:22, Bjorn Andersson wrote: > From: Bjorn Andersson > > Add Adreno SMMU, GPU clock controller, GMU and GPU nodes for the > SC8280XP. > > Tested-by: Steev Klimaszewski > Signed-off-by: Bjorn Andersson > Tested-by: Johan Hovold > Signed-off-by: Bjorn Andersson > --- Reviewed-by: Konrad Dybcio Konrad > arch/arm64/boot/dts/qcom/sa8540p.dtsi | 8 ++ > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 175 +++++++++++++++++++++++++ > 2 files changed, 183 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sa8540p.dtsi b/arch/arm64/boot/dts/qcom/sa8540p.dtsi > index 4a990fda8fc3..bacbdec56281 100644 > --- a/arch/arm64/boot/dts/qcom/sa8540p.dtsi > +++ b/arch/arm64/boot/dts/qcom/sa8540p.dtsi > @@ -167,6 +167,14 @@ opp-2592000000 { > }; > }; > > +&gpucc { > + status = "disabled"; > +}; > + > +&gpu_smmu { > + status = "disabled"; > +}; > + > &pcie2a { > compatible = "qcom,pcie-sa8540p"; > > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > index 6b1bb203b1d1..ac0596dfdbc4 100644 > --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > @@ -6,6 +6,7 @@ > > #include > #include > +#include > #include > #include > #include > @@ -2341,6 +2342,180 @@ tcsr: syscon@1fc0000 { > reg = <0x0 0x01fc0000 0x0 0x30000>; > }; > > + gpu: gpu@3d00000 { > + compatible = "qcom,adreno-690.0", "qcom,adreno"; > + > + reg = <0 0x03d00000 0 0x40000>, > + <0 0x03d9e000 0 0x1000>, > + <0 0x03d61000 0 0x800>; > + reg-names = "kgsl_3d0_reg_memory", > + "cx_mem", > + "cx_dbgc"; > + interrupts = ; > + iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>; > + operating-points-v2 = <&gpu_opp_table>; > + > + qcom,gmu = <&gmu>; > + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; > + interconnect-names = "gfx-mem"; > + #cooling-cells = <2>; > + > + status = "disabled"; > + > + gpu_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-270000000 { > + opp-hz = /bits/ 64 <270000000>; > + opp-level = ; > + opp-peak-kBps = <451000>; > + }; > + > + opp-410000000 { > + opp-hz = /bits/ 64 <410000000>; > + opp-level = ; > + opp-peak-kBps = <1555000>; > + }; > + > + opp-500000000 { > + opp-hz = /bits/ 64 <500000000>; > + opp-level = ; > + opp-peak-kBps = <1555000>; > + }; > + > + opp-547000000 { > + opp-hz = /bits/ 64 <547000000>; > + opp-level = ; > + opp-peak-kBps = <1555000>; > + }; > + > + opp-606000000 { > + opp-hz = /bits/ 64 <606000000>; > + opp-level = ; > + opp-peak-kBps = <2736000>; > + }; > + > + opp-640000000 { > + opp-hz = /bits/ 64 <640000000>; > + opp-level = ; > + opp-peak-kBps = <2736000>; > + }; > + > + opp-655000000 { > + opp-hz = /bits/ 64 <655000000>; > + opp-level = ; > + opp-peak-kBps = <2736000>; > + }; > + > + opp-690000000 { > + opp-hz = /bits/ 64 <690000000>; > + opp-level = ; > + opp-peak-kBps = <2736000>; > + }; > + }; > + }; > + > + gmu: gmu@3d6a000 { > + compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu"; > + reg = <0 0x03d6a000 0 0x34000>, > + <0 0x03de0000 0 0x10000>, > + <0 0x0b290000 0 0x10000>; > + reg-names = "gmu", "rscc", "gmu_pdc"; > + interrupts = , > + ; > + interrupt-names = "hfi", "gmu"; > + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, > + <&gpucc GPU_CC_CXO_CLK>, > + <&gcc GCC_DDRSS_GPU_AXI_CLK>, > + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, > + <&gpucc GPU_CC_AHB_CLK>, > + <&gpucc GPU_CC_HUB_CX_INT_CLK>, > + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; > + clock-names = "gmu", > + "cxo", > + "axi", > + "memnoc", > + "ahb", > + "hub", > + "smmu_vote"; > + power-domains = <&gpucc GPU_CC_CX_GDSC>, > + <&gpucc GPU_CC_GX_GDSC>; > + power-domain-names = "cx", > + "gx"; > + iommus = <&gpu_smmu 5 0xc00>; > + operating-points-v2 = <&gmu_opp_table>; > + > + gmu_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-200000000 { > + opp-hz = /bits/ 64 <200000000>; > + opp-level = ; > + }; > + > + opp-500000000 { > + opp-hz = /bits/ 64 <500000000>; > + opp-level = ; > + }; > + }; > + }; > + > + gpucc: clock-controller@3d90000 { > + compatible = "qcom,sc8280xp-gpucc"; > + reg = <0 0x03d90000 0 0x9000>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_GPU_GPLL0_CLK_SRC>, > + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; > + clock-names = "bi_tcxo", > + "gcc_gpu_gpll0_clk_src", > + "gcc_gpu_gpll0_div_clk_src"; > + > + power-domains = <&rpmhpd SC8280XP_GFX>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > + gpu_smmu: iommu@3da0000 { > + compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu", > + "qcom,smmu-500", "arm,mmu-500"; > + reg = <0 0x03da0000 0 0x20000>; > + #iommu-cells = <2>; > + #global-interrupts = <2>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + > + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, > + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, > + <&gpucc GPU_CC_AHB_CLK>, > + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, > + <&gpucc GPU_CC_CX_GMU_CLK>, > + <&gpucc GPU_CC_HUB_CX_INT_CLK>, > + <&gpucc GPU_CC_HUB_AON_CLK>; > + clock-names = "gcc_gpu_memnoc_gfx_clk", > + "gcc_gpu_snoc_dvm_gfx_clk", > + "gpu_cc_ahb_clk", > + "gpu_cc_hlos1_vote_gpu_smmu_clk", > + "gpu_cc_cx_gmu_clk", > + "gpu_cc_hub_cx_int_clk", > + "gpu_cc_hub_aon_clk"; > + > + power-domains = <&gpucc GPU_CC_CX_GDSC>; > + dma-coherent; > + }; > + > usb_0_hsphy: phy@88e5000 { > compatible = "qcom,sc8280xp-usb-hs-phy", > "qcom,usb-snps-hs-5nm-phy";