[PATCH v2 0/4] Add Airoha EN7581 PCIe support

[PATCH v2 0/4] Add Airoha EN7581 PCIe support

[Lorenzo Bianconi]

Introduce support for EN7581 SoC to mediatek-gen3 PCIe driver

Changes since v1:
- remove register magic values
- remove delay magic values
- cosmetics
- fix dts binding for clock/reset

Lorenzo Bianconi (4):
  dt-bindings: PCI: mediatek-gen3: add support for Airoha EN7581
  PCI: mediatek-gen3: Add mtk_gen3_pcie_pdata data structure
  PCI: mediatek-gen3: Rely on reset_bulk APIs for PHY reset lines
  PCI: mediatek-gen3: Add Airoha EN7581 support

 .../bindings/pci/mediatek-pcie-gen3.yaml      |  68 +++++++-
 drivers/pci/controller/Kconfig                |   2 +-
 drivers/pci/controller/pcie-mediatek-gen3.c   | 163 ++++++++++++++++--
 3 files changed, 212 insertions(+), 21 deletions(-)

-- 
2.45.2

[PATCH v2 1/4] dt-bindings: PCI: mediatek-gen3: add support for Airoha EN7581

[Lorenzo Bianconi]

Introduce Airoha EN7581 entry in mediatek-gen3 PCIe controller binding

Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
 .../bindings/pci/mediatek-pcie-gen3.yaml      | 68 +++++++++++++++++--
 1 file changed, 63 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
index 76d742051f73..59112adc9ba1 100644
--- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
@@ -53,6 +53,7 @@ properties:
               - mediatek,mt8195-pcie
           - const: mediatek,mt8192-pcie
       - const: mediatek,mt8192-pcie
+      - const: airoha,en7581-pcie
 
   reg:
     maxItems: 1
@@ -76,20 +77,20 @@ properties:
 
   resets:
     minItems: 1
-    maxItems: 2
+    maxItems: 3
 
   reset-names:
     minItems: 1
-    maxItems: 2
+    maxItems: 3
     items:
-      enum: [ phy, mac ]
+      enum: [ phy, mac, phy-lane0, phy-lane1, phy-lane2 ]
 
   clocks:
-    minItems: 4
+    minItems: 1
     maxItems: 6
 
   clock-names:
-    minItems: 4
+    minItems: 1
     maxItems: 6
 
   assigned-clocks:
@@ -147,6 +148,9 @@ allOf:
           const: mediatek,mt8192-pcie
     then:
       properties:
+        clocks:
+          maxItems: 6
+
         clock-names:
           items:
             - const: pl_250m
@@ -155,6 +159,15 @@ allOf:
             - const: tl_32k
             - const: peri_26m
             - const: top_133m
+
+        resets:
+          minItems: 1
+          maxItems: 2
+
+        reset-names:
+          minItems: 1
+          maxItems: 2
+
   - if:
       properties:
         compatible:
@@ -164,6 +177,9 @@ allOf:
               - mediatek,mt8195-pcie
     then:
       properties:
+        clocks:
+          maxItems: 6
+
         clock-names:
           items:
             - const: pl_250m
@@ -172,6 +188,15 @@ allOf:
             - const: tl_32k
             - const: peri_26m
             - const: peri_mem
+
+        resets:
+          minItems: 1
+          maxItems: 2
+
+        reset-names:
+          minItems: 1
+          maxItems: 2
+
   - if:
       properties:
         compatible:
@@ -180,6 +205,9 @@ allOf:
               - mediatek,mt7986-pcie
     then:
       properties:
+        clocks:
+          maxItems: 4
+
         clock-names:
           items:
             - const: pl_250m
@@ -187,6 +215,36 @@ allOf:
             - const: peri_26m
             - const: top_133m
 
+        resets:
+          minItems: 1
+          maxItems: 2
+
+        reset-names:
+          minItems: 1
+          maxItems: 2
+
+  - if:
+      properties:
+        compatible:
+          const: airoha,en7581-pcie
+    then:
+      properties:
+        clocks:
+          maxItems: 1
+
+        clock-names:
+          items:
+            - const: sys-ck
+
+        resets:
+          maxItems: 3
+
+        reset-names:
+          items:
+            - const: phy-lane0
+            - const: phy-lane1
+            - const: phy-lane2
+
 unevaluatedProperties: false
 
 examples:
-- 
2.45.2

Re: [PATCH v2 1/4] dt-bindings: PCI: mediatek-gen3: add support for Airoha EN7581

[Conor Dooley]

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On Thu, Jun 27, 2024 at 10:12:11AM +0200, Lorenzo Bianconi wrote:
> Introduce Airoha EN7581 entry in mediatek-gen3 PCIe controller binding
> 
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> ---
>  .../bindings/pci/mediatek-pcie-gen3.yaml      | 68 +++++++++++++++++--
>  1 file changed, 63 insertions(+), 5 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> index 76d742051f73..59112adc9ba1 100644
> --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> @@ -53,6 +53,7 @@ properties:
>                - mediatek,mt8195-pcie
>            - const: mediatek,mt8192-pcie
>        - const: mediatek,mt8192-pcie
> +      - const: airoha,en7581-pcie
>  
>    reg:
>      maxItems: 1
> @@ -76,20 +77,20 @@ properties:
>  
>    resets:
>      minItems: 1
> -    maxItems: 2
> +    maxItems: 3
>  
>    reset-names:
>      minItems: 1
> -    maxItems: 2
> +    maxItems: 3
>      items:
> -      enum: [ phy, mac ]
> +      enum: [ phy, mac, phy-lane0, phy-lane1, phy-lane2 ]
>  
>    clocks:
> -    minItems: 4
> +    minItems: 1
>      maxItems: 6
>  
>    clock-names:
> -    minItems: 4
> +    minItems: 1
>      maxItems: 6
>  
>    assigned-clocks:
> @@ -147,6 +148,9 @@ allOf:
>            const: mediatek,mt8192-pcie
>      then:
>        properties:
> +        clocks:
> +          maxItems: 6
> +
>          clock-names:
>            items:
>              - const: pl_250m
> @@ -155,6 +159,15 @@ allOf:
>              - const: tl_32k
>              - const: peri_26m
>              - const: top_133m
> +
> +        resets:
> +          minItems: 1
> +          maxItems: 2
> +
> +        reset-names:
> +          minItems: 1
> +          maxItems: 2
> +
>    - if:
>        properties:
>          compatible:
> @@ -164,6 +177,9 @@ allOf:
>                - mediatek,mt8195-pcie
>      then:
>        properties:
> +        clocks:
> +          maxItems: 6

How come this is maxItems and not minItems? The max is always 6, before
and after your patch.

Cheers,
Conor.

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Re: [PATCH v2 1/4] dt-bindings: PCI: mediatek-gen3: add support for Airoha EN7581

[Lorenzo Bianconi]

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> On Thu, Jun 27, 2024 at 10:12:11AM +0200, Lorenzo Bianconi wrote:
> > Introduce Airoha EN7581 entry in mediatek-gen3 PCIe controller binding
> > 
> > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> > ---
> >  .../bindings/pci/mediatek-pcie-gen3.yaml      | 68 +++++++++++++++++--
> >  1 file changed, 63 insertions(+), 5 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> > index 76d742051f73..59112adc9ba1 100644
> > --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> > @@ -53,6 +53,7 @@ properties:
> >                - mediatek,mt8195-pcie
> >            - const: mediatek,mt8192-pcie
> >        - const: mediatek,mt8192-pcie
> > +      - const: airoha,en7581-pcie
> >  
> >    reg:
> >      maxItems: 1
> > @@ -76,20 +77,20 @@ properties:
> >  
> >    resets:
> >      minItems: 1
> > -    maxItems: 2
> > +    maxItems: 3
> >  
> >    reset-names:
> >      minItems: 1
> > -    maxItems: 2
> > +    maxItems: 3
> >      items:
> > -      enum: [ phy, mac ]
> > +      enum: [ phy, mac, phy-lane0, phy-lane1, phy-lane2 ]
> >  
> >    clocks:
> > -    minItems: 4
> > +    minItems: 1
> >      maxItems: 6
> >  
> >    clock-names:
> > -    minItems: 4
> > +    minItems: 1
> >      maxItems: 6
> >  
> >    assigned-clocks:
> > @@ -147,6 +148,9 @@ allOf:
> >            const: mediatek,mt8192-pcie
> >      then:
> >        properties:
> > +        clocks:
> > +          maxItems: 6
> > +
> >          clock-names:
> >            items:
> >              - const: pl_250m
> > @@ -155,6 +159,15 @@ allOf:
> >              - const: tl_32k
> >              - const: peri_26m
> >              - const: top_133m
> > +
> > +        resets:
> > +          minItems: 1
> > +          maxItems: 2
> > +
> > +        reset-names:
> > +          minItems: 1
> > +          maxItems: 2
> > +
> >    - if:
> >        properties:
> >          compatible:
> > @@ -164,6 +177,9 @@ allOf:
> >                - mediatek,mt8195-pcie
> >      then:
> >        properties:
> > +        clocks:
> > +          maxItems: 6
> 
> How come this is maxItems and not minItems? The max is always 6, before
> and after your patch.

ack, I will fix in v3

Regards,
Lorenzo

> 
> Cheers,
> Conor.



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[PATCH v2 2/4] PCI: mediatek-gen3: Add mtk_gen3_pcie_pdata data structure

[Lorenzo Bianconi]

Introduce mtk_gen3_pcie_pdata data structure in order to define
multiple callbacks for each supported SoC. This is a preliminary
patch to introduce EN7581 PCIe support.

Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
 drivers/pci/controller/pcie-mediatek-gen3.c | 24 ++++++++++++++++++---
 1 file changed, 21 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
index 975b3024fb08..db0210803731 100644
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -100,6 +100,16 @@
 #define PCIE_ATR_TLP_TYPE_MEM		PCIE_ATR_TLP_TYPE(0)
 #define PCIE_ATR_TLP_TYPE_IO		PCIE_ATR_TLP_TYPE(2)
 
+struct mtk_gen3_pcie;
+
+/**
+ * struct mtk_gen3_pcie_pdata - differentiate between host generations
+ * @power_up: pcie power_up callback
+ */
+struct mtk_gen3_pcie_pdata {
+	int (*power_up)(struct mtk_gen3_pcie *pcie);
+};
+
 /**
  * struct mtk_msi_set - MSI information for each set
  * @base: IO mapped register base
@@ -131,6 +141,7 @@ struct mtk_msi_set {
  * @msi_sets: MSI sets information
  * @lock: lock protecting IRQ bit map
  * @msi_irq_in_use: bit map for assigned MSI IRQ
+ * @soc: pointer to SoC-dependent operations
  */
 struct mtk_gen3_pcie {
 	struct device *dev;
@@ -151,6 +162,8 @@ struct mtk_gen3_pcie {
 	struct mtk_msi_set msi_sets[PCIE_MSI_SET_NUM];
 	struct mutex lock;
 	DECLARE_BITMAP(msi_irq_in_use, PCIE_MSI_IRQS_NUM);
+
+	const struct mtk_gen3_pcie_pdata *soc;
 };
 
 /* LTSSM state in PCIE_LTSSM_STATUS_REG bit[28:24] */
@@ -904,7 +917,7 @@ static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
 	usleep_range(10, 20);
 
 	/* Don't touch the hardware registers before power up */
-	err = mtk_pcie_power_up(pcie);
+	err = pcie->soc->power_up(pcie);
 	if (err)
 		return err;
 
@@ -939,6 +952,7 @@ static int mtk_pcie_probe(struct platform_device *pdev)
 	pcie = pci_host_bridge_priv(host);
 
 	pcie->dev = dev;
+	pcie->soc = device_get_match_data(dev);
 	platform_set_drvdata(pdev, pcie);
 
 	err = mtk_pcie_setup(pcie);
@@ -1054,7 +1068,7 @@ static int mtk_pcie_resume_noirq(struct device *dev)
 	struct mtk_gen3_pcie *pcie = dev_get_drvdata(dev);
 	int err;
 
-	err = mtk_pcie_power_up(pcie);
+	err = pcie->soc->power_up(pcie);
 	if (err)
 		return err;
 
@@ -1074,8 +1088,12 @@ static const struct dev_pm_ops mtk_pcie_pm_ops = {
 				  mtk_pcie_resume_noirq)
 };
 
+static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_mt8192 = {
+	.power_up = mtk_pcie_power_up,
+};
+
 static const struct of_device_id mtk_pcie_of_match[] = {
-	{ .compatible = "mediatek,mt8192-pcie" },
+	{ .compatible = "mediatek,mt8192-pcie", .data = &mtk_pcie_soc_mt8192 },
 	{},
 };
 MODULE_DEVICE_TABLE(of, mtk_pcie_of_match);
-- 
2.45.2

Re: [PATCH v2 2/4] PCI: mediatek-gen3: Add mtk_gen3_pcie_pdata data structure

[AngeloGioacchino Del Regno]

Il 27/06/24 10:12, Lorenzo Bianconi ha scritto:
> Introduce mtk_gen3_pcie_pdata data structure in order to define
> multiple callbacks for each supported SoC. This is a preliminary
> patch to introduce EN7581 PCIe support.
> 
> Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

[PATCH v2 3/4] PCI: mediatek-gen3: Rely on reset_bulk APIs for PHY reset lines

[Lorenzo Bianconi]

Use reset_bulk APIs to manage PHY reset lines. This is a preliminary
patch in order to add Airoha EN7581 PCIe support.

Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
 drivers/pci/controller/pcie-mediatek-gen3.c | 45 +++++++++++++++------
 1 file changed, 33 insertions(+), 12 deletions(-)

diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
index db0210803731..438a5222d986 100644
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -100,14 +100,21 @@
 #define PCIE_ATR_TLP_TYPE_MEM		PCIE_ATR_TLP_TYPE(0)
 #define PCIE_ATR_TLP_TYPE_IO		PCIE_ATR_TLP_TYPE(2)
 
+#define MAX_NUM_PHY_RESETS		1
+
 struct mtk_gen3_pcie;
 
 /**
  * struct mtk_gen3_pcie_pdata - differentiate between host generations
  * @power_up: pcie power_up callback
+ * @phy_resets: phy reset lines SoC data.
  */
 struct mtk_gen3_pcie_pdata {
 	int (*power_up)(struct mtk_gen3_pcie *pcie);
+	struct {
+		const char *id[MAX_NUM_PHY_RESETS];
+		int num_resets;
+	} phy_resets;
 };
 
 /**
@@ -128,7 +135,7 @@ struct mtk_msi_set {
  * @base: IO mapped register base
  * @reg_base: physical register base
  * @mac_reset: MAC reset control
- * @phy_reset: PHY reset control
+ * @phy_resets: PHY reset controllers
  * @phy: PHY controller block
  * @clks: PCIe clocks
  * @num_clks: PCIe clocks count for this port
@@ -148,7 +155,7 @@ struct mtk_gen3_pcie {
 	void __iomem *base;
 	phys_addr_t reg_base;
 	struct reset_control *mac_reset;
-	struct reset_control *phy_reset;
+	struct reset_control_bulk_data phy_resets[MAX_NUM_PHY_RESETS];
 	struct phy *phy;
 	struct clk_bulk_data *clks;
 	int num_clks;
@@ -788,10 +795,10 @@ static int mtk_pcie_setup_irq(struct mtk_gen3_pcie *pcie)
 
 static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
 {
+	int i, ret, num_resets = pcie->soc->phy_resets.num_resets;
 	struct device *dev = pcie->dev;
 	struct platform_device *pdev = to_platform_device(dev);
 	struct resource *regs;
-	int ret;
 
 	regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac");
 	if (!regs)
@@ -804,12 +811,12 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
 
 	pcie->reg_base = regs->start;
 
-	pcie->phy_reset = devm_reset_control_get_optional_exclusive(dev, "phy");
-	if (IS_ERR(pcie->phy_reset)) {
-		ret = PTR_ERR(pcie->phy_reset);
-		if (ret != -EPROBE_DEFER)
-			dev_err(dev, "failed to get PHY reset\n");
+	for (i = 0; i < num_resets; i++)
+		pcie->phy_resets[i].id = pcie->soc->phy_resets.id[i];
 
+	ret = devm_reset_control_bulk_get_optional_shared(dev, num_resets, pcie->phy_resets);
+	if (ret) {
+		dev_err(dev, "failed to get PHY bulk reset\n");
 		return ret;
 	}
 
@@ -846,7 +853,11 @@ static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie)
 	int err;
 
 	/* PHY power on and enable pipe clock */
-	reset_control_deassert(pcie->phy_reset);
+	err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
+	if (err) {
+		dev_err(dev, "failed to deassert PHYs\n");
+		return err;
+	}
 
 	err = phy_init(pcie->phy);
 	if (err) {
@@ -882,7 +893,7 @@ static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie)
 err_phy_on:
 	phy_exit(pcie->phy);
 err_phy_init:
-	reset_control_assert(pcie->phy_reset);
+	reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
 
 	return err;
 }
@@ -897,7 +908,7 @@ static void mtk_pcie_power_down(struct mtk_gen3_pcie *pcie)
 
 	phy_power_off(pcie->phy);
 	phy_exit(pcie->phy);
-	reset_control_assert(pcie->phy_reset);
+	reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
 }
 
 static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
@@ -908,11 +919,17 @@ static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
 	if (err)
 		return err;
 
+	/*
+	 * Deassert the line in order to avoid unbalance in deassert_count
+	 * counter since the bulk is shared.
+	 */
+	reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
 	/*
 	 * The controller may have been left out of reset by the bootloader
 	 * so make sure that we get a clean start by asserting resets here.
 	 */
-	reset_control_assert(pcie->phy_reset);
+	reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
+
 	reset_control_assert(pcie->mac_reset);
 	usleep_range(10, 20);
 
@@ -1090,6 +1107,10 @@ static const struct dev_pm_ops mtk_pcie_pm_ops = {
 
 static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_mt8192 = {
 	.power_up = mtk_pcie_power_up,
+	.phy_resets = {
+		.id[0] = "phy",
+		.num_resets = 1,
+	},
 };
 
 static const struct of_device_id mtk_pcie_of_match[] = {
-- 
2.45.2

Re: [PATCH v2 3/4] PCI: mediatek-gen3: Rely on reset_bulk APIs for PHY reset lines

[AngeloGioacchino Del Regno]

Il 27/06/24 10:12, Lorenzo Bianconi ha scritto:
> Use reset_bulk APIs to manage PHY reset lines. This is a preliminary
> patch in order to add Airoha EN7581 PCIe support.
> 
> Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

[PATCH v2 4/4] PCI: mediatek-gen3: Add Airoha EN7581 support

[Lorenzo Bianconi]

Introduce support for Airoha EN7581 PCIe controller to mediatek-gen3
PCIe controller driver.

Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
 drivers/pci/controller/Kconfig              |  2 +-
 drivers/pci/controller/pcie-mediatek-gen3.c | 96 ++++++++++++++++++++-
 2 files changed, 96 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index e534c02ee34f..3bd6c9430010 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -196,7 +196,7 @@ config PCIE_MEDIATEK
 
 config PCIE_MEDIATEK_GEN3
 	tristate "MediaTek Gen3 PCIe controller"
-	depends on ARCH_MEDIATEK || COMPILE_TEST
+	depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST
 	depends on PCI_MSI
 	help
 	  Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.
diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
index 438a5222d986..af567b4355fa 100644
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -7,6 +7,7 @@
  */
 
 #include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/delay.h>
 #include <linux/iopoll.h>
 #include <linux/irq.h>
@@ -15,6 +16,8 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/msi.h>
+#include <linux/of_device.h>
+#include <linux/of_pci.h>
 #include <linux/pci.h>
 #include <linux/phy/phy.h>
 #include <linux/platform_device.h>
@@ -29,6 +32,7 @@
 #define PCI_CLASS(class)		(class << 8)
 #define PCIE_RC_MODE			BIT(0)
 
+#define PCIE_EQ_PRESET_01_REF		0x100
 #define PCIE_CFGNUM_REG			0x140
 #define PCIE_CFG_DEVFN(devfn)		((devfn) & GENMASK(7, 0))
 #define PCIE_CFG_BUS(bus)		(((bus) << 8) & GENMASK(15, 8))
@@ -68,6 +72,7 @@
 #define PCIE_MSI_SET_ENABLE_REG		0x190
 #define PCIE_MSI_SET_ENABLE		GENMASK(PCIE_MSI_SET_NUM - 1, 0)
 
+#define PCIE_PIPE4_PIE8_REG		0x338
 #define PCIE_MSI_SET_BASE_REG		0xc00
 #define PCIE_MSI_SET_OFFSET		0x10
 #define PCIE_MSI_SET_STATUS_OFFSET	0x04
@@ -100,7 +105,17 @@
 #define PCIE_ATR_TLP_TYPE_MEM		PCIE_ATR_TLP_TYPE(0)
 #define PCIE_ATR_TLP_TYPE_IO		PCIE_ATR_TLP_TYPE(2)
 
-#define MAX_NUM_PHY_RESETS		1
+/* EN7581 */
+#define PCIE_PEXTP_DIG_GLB44_P0_REG	0x10044
+#define PCIE_PEXTP_DIG_LN_RX30_P0_REG	0x15030
+#define PCIE_PEXTP_DIG_LN_RX30_P1_REG	0x15130
+
+/* PCIe-PHY initialization delay in ms */
+#define PHY_INIT_TIME_MS		30
+/* PCIe reset line delay in ms */
+#define PCIE_RESET_TIME_MS		100
+
+#define MAX_NUM_PHY_RESETS		3
 
 struct mtk_gen3_pcie;
 
@@ -847,6 +862,74 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
 	return 0;
 }
 
+static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie)
+{
+	struct device *dev = pcie->dev;
+	int err;
+
+	/* Wait for bulk assert completion in mtk_pcie_setup */
+	mdelay(PCIE_RESET_TIME_MS);
+
+	/* Setup Tx-Rx detect time */
+	writel_relaxed(0x23020133, pcie->base + PCIE_PEXTP_DIG_GLB44_P0_REG);
+	/* Setup Rx AEQ training time */
+	writel_relaxed(0x50500032, pcie->base + PCIE_PEXTP_DIG_LN_RX30_P0_REG);
+	writel_relaxed(0x50500032, pcie->base + PCIE_PEXTP_DIG_LN_RX30_P1_REG);
+
+	err = phy_init(pcie->phy);
+	if (err) {
+		dev_err(dev, "failed to initialize PHY\n");
+		return err;
+	}
+	mdelay(PHY_INIT_TIME_MS);
+
+	err = phy_power_on(pcie->phy);
+	if (err) {
+		dev_err(dev, "failed to power on PHY\n");
+		goto err_phy_on;
+	}
+
+	err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
+	if (err) {
+		dev_err(dev, "failed to deassert PHYs\n");
+		goto err_phy_deassert;
+	}
+	mdelay(PCIE_RESET_TIME_MS);
+
+	pm_runtime_enable(dev);
+	pm_runtime_get_sync(dev);
+
+	err = clk_bulk_prepare(pcie->num_clks, pcie->clks);
+	if (err) {
+		dev_err(dev, "failed to prepare clock\n");
+		goto err_clk_prepare;
+	}
+
+	writel_relaxed(0x41474147, pcie->base + PCIE_EQ_PRESET_01_REF);
+	writel_relaxed(0x1018020f, pcie->base + PCIE_PIPE4_PIE8_REG);
+
+	err = clk_bulk_enable(pcie->num_clks, pcie->clks);
+	if (err) {
+		dev_err(dev, "failed to prepare clock\n");
+		goto err_clk_enable;
+	}
+
+	return 0;
+
+err_clk_enable:
+	clk_bulk_unprepare(pcie->num_clks, pcie->clks);
+err_clk_prepare:
+	pm_runtime_put_sync(dev);
+	pm_runtime_disable(dev);
+	reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
+err_phy_deassert:
+	phy_power_off(pcie->phy);
+err_phy_on:
+	phy_exit(pcie->phy);
+
+	return err;
+}
+
 static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie)
 {
 	struct device *dev = pcie->dev;
@@ -1113,8 +1196,19 @@ static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_mt8192 = {
 	},
 };
 
+static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_en7581 = {
+	.power_up = mtk_pcie_en7581_power_up,
+	.phy_resets = {
+		.id[0] = "phy-lane0",
+		.id[1] = "phy-lane1",
+		.id[2] = "phy-lane2",
+		.num_resets = 3,
+	},
+};
+
 static const struct of_device_id mtk_pcie_of_match[] = {
 	{ .compatible = "mediatek,mt8192-pcie", .data = &mtk_pcie_soc_mt8192 },
+	{ .compatible = "airoha,en7581-pcie", .data = &mtk_pcie_soc_en7581 },
 	{},
 };
 MODULE_DEVICE_TABLE(of, mtk_pcie_of_match);
-- 
2.45.2

Re: [PATCH v2 4/4] PCI: mediatek-gen3: Add Airoha EN7581 support

[AngeloGioacchino Del Regno]

Il 27/06/24 10:12, Lorenzo Bianconi ha scritto:
> Introduce support for Airoha EN7581 PCIe controller to mediatek-gen3
> PCIe controller driver.
> 
> Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> ---
>   drivers/pci/controller/Kconfig              |  2 +-
>   drivers/pci/controller/pcie-mediatek-gen3.c | 96 ++++++++++++++++++++-
>   2 files changed, 96 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> index e534c02ee34f..3bd6c9430010 100644
> --- a/drivers/pci/controller/Kconfig
> +++ b/drivers/pci/controller/Kconfig
> @@ -196,7 +196,7 @@ config PCIE_MEDIATEK
>   
>   config PCIE_MEDIATEK_GEN3
>   	tristate "MediaTek Gen3 PCIe controller"
> -	depends on ARCH_MEDIATEK || COMPILE_TEST
> +	depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST
>   	depends on PCI_MSI
>   	help
>   	  Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.
> diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
> index 438a5222d986..af567b4355fa 100644
> --- a/drivers/pci/controller/pcie-mediatek-gen3.c
> +++ b/drivers/pci/controller/pcie-mediatek-gen3.c

..snip..

> +
>   static const struct of_device_id mtk_pcie_of_match[] = {
>   	{ .compatible = "mediatek,mt8192-pcie", .data = &mtk_pcie_soc_mt8192 },
> +	{ .compatible = "airoha,en7581-pcie", .data = &mtk_pcie_soc_en7581 },

My bad, in the last review I didn't notice that the ordering here is not good.

A ... iroha comes before
M ... ediatek :-)

Please put the airoha entry before the mediatek one, after which:

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

>   	{},
>   };
>   MODULE_DEVICE_TABLE(of, mtk_pcie_of_match);

Re: [PATCH v2 4/4] PCI: mediatek-gen3: Add Airoha EN7581 support

[Jianjun Wang (王建军)]

Hi Lorenzo,

On Thu, 2024-06-27 at 10:12 +0200, Lorenzo Bianconi wrote:
>  	 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>  Introduce support for Airoha EN7581 PCIe controller to mediatek-gen3
> PCIe controller driver.
> 
> Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> ---
>  drivers/pci/controller/Kconfig              |  2 +-
>  drivers/pci/controller/pcie-mediatek-gen3.c | 96
> ++++++++++++++++++++-
>  2 files changed, 96 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/controller/Kconfig
> b/drivers/pci/controller/Kconfig
> index e534c02ee34f..3bd6c9430010 100644
> --- a/drivers/pci/controller/Kconfig
> +++ b/drivers/pci/controller/Kconfig
> @@ -196,7 +196,7 @@ config PCIE_MEDIATEK
>  
>  config PCIE_MEDIATEK_GEN3
>  	tristate "MediaTek Gen3 PCIe controller"
> -	depends on ARCH_MEDIATEK || COMPILE_TEST
> +	depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST
>  	depends on PCI_MSI
>  	help
>  	  Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.
> diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c
> b/drivers/pci/controller/pcie-mediatek-gen3.c
> index 438a5222d986..af567b4355fa 100644
> --- a/drivers/pci/controller/pcie-mediatek-gen3.c
> +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> @@ -7,6 +7,7 @@
>   */
>  
>  #include <linux/clk.h>
> +#include <linux/clk-provider.h>
>  #include <linux/delay.h>
>  #include <linux/iopoll.h>
>  #include <linux/irq.h>
> @@ -15,6 +16,8 @@
>  #include <linux/kernel.h>
>  #include <linux/module.h>
>  #include <linux/msi.h>
> +#include <linux/of_device.h>
> +#include <linux/of_pci.h>
>  #include <linux/pci.h>
>  #include <linux/phy/phy.h>
>  #include <linux/platform_device.h>
> @@ -29,6 +32,7 @@
>  #define PCI_CLASS(class)		(class << 8)
>  #define PCIE_RC_MODE			BIT(0)
>  
> +#define PCIE_EQ_PRESET_01_REF		0x100
Should be PCIE_EQ_PRESET_01_REG

>  #define PCIE_CFGNUM_REG			0x140
>  #define PCIE_CFG_DEVFN(devfn)		((devfn) & GENMASK(7,
> 0))
>  #define PCIE_CFG_BUS(bus)		(((bus) << 8) & GENMASK(15, 8))
> @@ -68,6 +72,7 @@
>  #define PCIE_MSI_SET_ENABLE_REG		0x190
>  #define PCIE_MSI_SET_ENABLE		GENMASK(PCIE_MSI_SET_NUM - 1,
> 0)
>  
> +#define PCIE_PIPE4_PIE8_REG		0x338
>  #define PCIE_MSI_SET_BASE_REG		0xc00
>  #define PCIE_MSI_SET_OFFSET		0x10
>  #define PCIE_MSI_SET_STATUS_OFFSET	0x04
> @@ -100,7 +105,17 @@
>  #define PCIE_ATR_TLP_TYPE_MEM		PCIE_ATR_TLP_TYPE(0)
>  #define PCIE_ATR_TLP_TYPE_IO		PCIE_ATR_TLP_TYPE(2)
>  
> -#define MAX_NUM_PHY_RESETS		1
> +/* EN7581 */
> +#define PCIE_PEXTP_DIG_GLB44_P0_REG	0x10044
> +#define PCIE_PEXTP_DIG_LN_RX30_P0_REG	0x15030
> +#define PCIE_PEXTP_DIG_LN_RX30_P1_REG	0x15130
These registers belong to PHY, I think they should be added in the phy
driver, which is located at drivers/phy/mediatek/phy-mtk-pcie.c.

> +
> +/* PCIe-PHY initialization delay in ms */
> +#define PHY_INIT_TIME_MS		30
> +/* PCIe reset line delay in ms */
> +#define PCIE_RESET_TIME_MS		100
> +
> +#define MAX_NUM_PHY_RESETS		3
>  
>  struct mtk_gen3_pcie;
>  
> @@ -847,6 +862,74 @@ static int mtk_pcie_parse_port(struct
> mtk_gen3_pcie *pcie)
>  	return 0;
>  }
>  
> +static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie)
> +{
> +	struct device *dev = pcie->dev;
> +	int err;
> +
> +	/* Wait for bulk assert completion in mtk_pcie_setup */
> +	mdelay(PCIE_RESET_TIME_MS);
> +
> +	/* Setup Tx-Rx detect time */
> +	writel_relaxed(0x23020133, pcie->base +
> PCIE_PEXTP_DIG_GLB44_P0_REG);
Please also add definitions for each field, the layout for
PCIE_PEXTP_DIG_GLB44_P0_REG is:
Bit[7:0] 
  Name: rg_xtp_rxdet_vcm_off_stb_t_sel
  Description: Stable Time Selection of tx_cmkp_en De-Assert (DC Common
Mode Turn-Off) During RX Detection, unit: 4 us
Bit[15:8]
  Name: rg_xtp_rxdet_en_stb_t_sel
  Description: Stable Time Selection of tx_rxdet_en Assert During RX
Detection, unit: 1 us
Bit[23:16]
  Name: rg_xtp_rxdet_finish_stb_t_sel
  Description: rxdet finish stable time selection, unit: 1 tx250m_ck
Bit[27:24]
  Name: rg_xtp_txpd_tx_data_en_dly
  Description: ckpd_tx_data_en_sync delay selection, unit: 1 tx250m_ck
Bit[28:28]
  Name: rg_xtp_txpd_rxdet_done_cdt
  Description: rxdet_done cdt selection, 0: !pipe_tx_detect_rx  1:
pipe_phy_status
Bit[31:29]
  Name: rg_xtp_rxdet_latch_stb_t_sel
  Description: rxdet_latch state stable time selection, unit: 1
tx250m_ck

> +	/* Setup Rx AEQ training time */
> +	writel_relaxed(0x50500032, pcie->base +
> PCIE_PEXTP_DIG_LN_RX30_P0_REG);
> +	writel_relaxed(0x50500032, pcie->base +
> PCIE_PEXTP_DIG_LN_RX30_P1_REG);
Layout for PEXTP_DIG_LN_RX30:
Bit[7:0] rg_xtp_ln_rx_pdown_l1p2_exit_wait_cnt
Bit[8] rg_xtp_ln_rx_pdown_t2rlb_dig_en
Bit[28:16] rg_xtp_ln_rx_pdown_e0_aeqen_wait_us

> +
> +	err = phy_init(pcie->phy);
> +	if (err) {
> +		dev_err(dev, "failed to initialize PHY\n");
> +		return err;
> +	}
> +	mdelay(PHY_INIT_TIME_MS);
> +
> +	err = phy_power_on(pcie->phy);
> +	if (err) {
> +		dev_err(dev, "failed to power on PHY\n");
> +		goto err_phy_on;
> +	}
> +
> +	err = reset_control_bulk_deassert(pcie->soc-
> >phy_resets.num_resets, pcie->phy_resets);
> +	if (err) {
> +		dev_err(dev, "failed to deassert PHYs\n");
> +		goto err_phy_deassert;
> +	}
> +	mdelay(PCIE_RESET_TIME_MS);
> +
> +	pm_runtime_enable(dev);
> +	pm_runtime_get_sync(dev);
> +
> +	err = clk_bulk_prepare(pcie->num_clks, pcie->clks);
> +	if (err) {
> +		dev_err(dev, "failed to prepare clock\n");
> +		goto err_clk_prepare;
> +	}
> +
> +	writel_relaxed(0x41474147, pcie->base + PCIE_EQ_PRESET_01_REF);
Bit[6:0] val_ln0_dn
  Bit [3:0]: Downstream port transmitter preset
  Bit [6:4]: Downstream port receiver preset hint
Bit[14:8] val_ln0_up
  Bit [11:8]: Upstream port transmitter preset
  Bit [14:12]: Upstream port receiver preset hint
Bit[22:16] val_ln1_dn
  Bit [19:16]: Downstream port transmitter preset
  Bit [22:20]: Downstream port receiver preset hint
BIt[30:24] val_ln1_up
  Bit [27:24]: Upstream port transmitter preset
  Bit [30:28]: Upstream port receiver preset hint

> +	writel_relaxed(0x1018020f, pcie->base + PCIE_PIPE4_PIE8_REG);
Bit[5:0] k_finetune_max
Bit[7:6] k_finetune_err
Bit[18:8] k_preset_to_use
Bit[19:19] k_phyparam_query
Bit[20:20] k_query_timeout
Bit[31:21] k_preset_to_use_16g

Thanks.

> +
> +	err = clk_bulk_enable(pcie->num_clks, pcie->clks);
> +	if (err) {
> +		dev_err(dev, "failed to prepare clock\n");
> +		goto err_clk_enable;
> +	}
> +
> +	return 0;
> +
> +err_clk_enable:
> +	clk_bulk_unprepare(pcie->num_clks, pcie->clks);
> +err_clk_prepare:
> +	pm_runtime_put_sync(dev);
> +	pm_runtime_disable(dev);
> +	reset_control_bulk_assert(pcie->soc->phy_resets.num_resets,
> pcie->phy_resets);
> +err_phy_deassert:
> +	phy_power_off(pcie->phy);
> +err_phy_on:
> +	phy_exit(pcie->phy);
> +
> +	return err;
> +}
> +
>  static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie)
>  {
>  	struct device *dev = pcie->dev;
> @@ -1113,8 +1196,19 @@ static const struct mtk_gen3_pcie_pdata
> mtk_pcie_soc_mt8192 = {
>  	},
>  };
>  
> +static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_en7581 = {
> +	.power_up = mtk_pcie_en7581_power_up,
> +	.phy_resets = {
> +		.id[0] = "phy-lane0",
> +		.id[1] = "phy-lane1",
> +		.id[2] = "phy-lane2",
> +		.num_resets = 3,
> +	},
> +};
> +
>  static const struct of_device_id mtk_pcie_of_match[] = {
>  	{ .compatible = "mediatek,mt8192-pcie", .data =
> &mtk_pcie_soc_mt8192 },
> +	{ .compatible = "airoha,en7581-pcie", .data =
> &mtk_pcie_soc_en7581 },
>  	{},
>  };
>  MODULE_DEVICE_TABLE(of, mtk_pcie_of_match);
> -- 
> 2.45.2
> 

Re: [PATCH v2 4/4] PCI: mediatek-gen3: Add Airoha EN7581 support

[lorenzo]

[-- Attachment #1: Type: text/plain, Size: 8555 bytes --]

> Hi Lorenzo,

Hi Jianjun,

> 
> On Thu, 2024-06-27 at 10:12 +0200, Lorenzo Bianconi wrote:
> >  	 
> > External email : Please do not click links or open attachments until
> > you have verified the sender or the content.
> >  Introduce support for Airoha EN7581 PCIe controller to mediatek-gen3
> > PCIe controller driver.
> > 
> > Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
> > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> > ---
> >  drivers/pci/controller/Kconfig              |  2 +-
> >  drivers/pci/controller/pcie-mediatek-gen3.c | 96
> > ++++++++++++++++++++-
> >  2 files changed, 96 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/pci/controller/Kconfig
> > b/drivers/pci/controller/Kconfig
> > index e534c02ee34f..3bd6c9430010 100644
> > --- a/drivers/pci/controller/Kconfig
> > +++ b/drivers/pci/controller/Kconfig
> > @@ -196,7 +196,7 @@ config PCIE_MEDIATEK
> >  
> >  config PCIE_MEDIATEK_GEN3
> >  	tristate "MediaTek Gen3 PCIe controller"
> > -	depends on ARCH_MEDIATEK || COMPILE_TEST
> > +	depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST
> >  	depends on PCI_MSI
> >  	help
> >  	  Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.
> > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c
> > b/drivers/pci/controller/pcie-mediatek-gen3.c
> > index 438a5222d986..af567b4355fa 100644
> > --- a/drivers/pci/controller/pcie-mediatek-gen3.c
> > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> > @@ -7,6 +7,7 @@
> >   */
> >  
> >  #include <linux/clk.h>
> > +#include <linux/clk-provider.h>
> >  #include <linux/delay.h>
> >  #include <linux/iopoll.h>
> >  #include <linux/irq.h>
> > @@ -15,6 +16,8 @@
> >  #include <linux/kernel.h>
> >  #include <linux/module.h>
> >  #include <linux/msi.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_pci.h>
> >  #include <linux/pci.h>
> >  #include <linux/phy/phy.h>
> >  #include <linux/platform_device.h>
> > @@ -29,6 +32,7 @@
> >  #define PCI_CLASS(class)		(class << 8)
> >  #define PCIE_RC_MODE			BIT(0)
> >  
> > +#define PCIE_EQ_PRESET_01_REF		0x100
> Should be PCIE_EQ_PRESET_01_REG

ack, I will fix it in v3.

> 
> >  #define PCIE_CFGNUM_REG			0x140
> >  #define PCIE_CFG_DEVFN(devfn)		((devfn) & GENMASK(7,
> > 0))
> >  #define PCIE_CFG_BUS(bus)		(((bus) << 8) & GENMASK(15, 8))
> > @@ -68,6 +72,7 @@
> >  #define PCIE_MSI_SET_ENABLE_REG		0x190
> >  #define PCIE_MSI_SET_ENABLE		GENMASK(PCIE_MSI_SET_NUM - 1,
> > 0)
> >  
> > +#define PCIE_PIPE4_PIE8_REG		0x338
> >  #define PCIE_MSI_SET_BASE_REG		0xc00
> >  #define PCIE_MSI_SET_OFFSET		0x10
> >  #define PCIE_MSI_SET_STATUS_OFFSET	0x04
> > @@ -100,7 +105,17 @@
> >  #define PCIE_ATR_TLP_TYPE_MEM		PCIE_ATR_TLP_TYPE(0)
> >  #define PCIE_ATR_TLP_TYPE_IO		PCIE_ATR_TLP_TYPE(2)
> >  
> > -#define MAX_NUM_PHY_RESETS		1
> > +/* EN7581 */
> > +#define PCIE_PEXTP_DIG_GLB44_P0_REG	0x10044
> > +#define PCIE_PEXTP_DIG_LN_RX30_P0_REG	0x15030
> > +#define PCIE_PEXTP_DIG_LN_RX30_P1_REG	0x15130
> These registers belong to PHY, I think they should be added in the phy
> driver, which is located at drivers/phy/mediatek/phy-mtk-pcie.c.

ack, I will move this configuration in the pcie-phy driver.

> 
> > +
> > +/* PCIe-PHY initialization delay in ms */
> > +#define PHY_INIT_TIME_MS		30
> > +/* PCIe reset line delay in ms */
> > +#define PCIE_RESET_TIME_MS		100
> > +
> > +#define MAX_NUM_PHY_RESETS		3
> >  
> >  struct mtk_gen3_pcie;
> >  
> > @@ -847,6 +862,74 @@ static int mtk_pcie_parse_port(struct
> > mtk_gen3_pcie *pcie)
> >  	return 0;
> >  }
> >  
> > +static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie)
> > +{
> > +	struct device *dev = pcie->dev;
> > +	int err;
> > +
> > +	/* Wait for bulk assert completion in mtk_pcie_setup */
> > +	mdelay(PCIE_RESET_TIME_MS);
> > +
> > +	/* Setup Tx-Rx detect time */
> > +	writel_relaxed(0x23020133, pcie->base +
> > PCIE_PEXTP_DIG_GLB44_P0_REG);
> Please also add definitions for each field, the layout for
> PCIE_PEXTP_DIG_GLB44_P0_REG is:
> Bit[7:0] 
>   Name: rg_xtp_rxdet_vcm_off_stb_t_sel
>   Description: Stable Time Selection of tx_cmkp_en De-Assert (DC Common
> Mode Turn-Off) During RX Detection, unit: 4 us
> Bit[15:8]
>   Name: rg_xtp_rxdet_en_stb_t_sel
>   Description: Stable Time Selection of tx_rxdet_en Assert During RX
> Detection, unit: 1 us
> Bit[23:16]
>   Name: rg_xtp_rxdet_finish_stb_t_sel
>   Description: rxdet finish stable time selection, unit: 1 tx250m_ck
> Bit[27:24]
>   Name: rg_xtp_txpd_tx_data_en_dly
>   Description: ckpd_tx_data_en_sync delay selection, unit: 1 tx250m_ck
> Bit[28:28]
>   Name: rg_xtp_txpd_rxdet_done_cdt
>   Description: rxdet_done cdt selection, 0: !pipe_tx_detect_rx  1:
> pipe_phy_status
> Bit[31:29]
>   Name: rg_xtp_rxdet_latch_stb_t_sel
>   Description: rxdet_latch state stable time selection, unit: 1
> tx250m_ck
> 
> > +	/* Setup Rx AEQ training time */
> > +	writel_relaxed(0x50500032, pcie->base +
> > PCIE_PEXTP_DIG_LN_RX30_P0_REG);
> > +	writel_relaxed(0x50500032, pcie->base +
> > PCIE_PEXTP_DIG_LN_RX30_P1_REG);
> Layout for PEXTP_DIG_LN_RX30:
> Bit[7:0] rg_xtp_ln_rx_pdown_l1p2_exit_wait_cnt
> Bit[8] rg_xtp_ln_rx_pdown_t2rlb_dig_en
> Bit[28:16] rg_xtp_ln_rx_pdown_e0_aeqen_wait_us
> 
> > +
> > +	err = phy_init(pcie->phy);
> > +	if (err) {
> > +		dev_err(dev, "failed to initialize PHY\n");
> > +		return err;
> > +	}
> > +	mdelay(PHY_INIT_TIME_MS);
> > +
> > +	err = phy_power_on(pcie->phy);
> > +	if (err) {
> > +		dev_err(dev, "failed to power on PHY\n");
> > +		goto err_phy_on;
> > +	}
> > +
> > +	err = reset_control_bulk_deassert(pcie->soc-
> > >phy_resets.num_resets, pcie->phy_resets);
> > +	if (err) {
> > +		dev_err(dev, "failed to deassert PHYs\n");
> > +		goto err_phy_deassert;
> > +	}
> > +	mdelay(PCIE_RESET_TIME_MS);
> > +
> > +	pm_runtime_enable(dev);
> > +	pm_runtime_get_sync(dev);
> > +
> > +	err = clk_bulk_prepare(pcie->num_clks, pcie->clks);
> > +	if (err) {
> > +		dev_err(dev, "failed to prepare clock\n");
> > +		goto err_clk_prepare;
> > +	}
> > +
> > +	writel_relaxed(0x41474147, pcie->base + PCIE_EQ_PRESET_01_REF);
> Bit[6:0] val_ln0_dn
>   Bit [3:0]: Downstream port transmitter preset
>   Bit [6:4]: Downstream port receiver preset hint
> Bit[14:8] val_ln0_up
>   Bit [11:8]: Upstream port transmitter preset
>   Bit [14:12]: Upstream port receiver preset hint
> Bit[22:16] val_ln1_dn
>   Bit [19:16]: Downstream port transmitter preset
>   Bit [22:20]: Downstream port receiver preset hint
> BIt[30:24] val_ln1_up
>   Bit [27:24]: Upstream port transmitter preset
>   Bit [30:28]: Upstream port receiver preset hint
> 
> > +	writel_relaxed(0x1018020f, pcie->base + PCIE_PIPE4_PIE8_REG);
> Bit[5:0] k_finetune_max
> Bit[7:6] k_finetune_err
> Bit[18:8] k_preset_to_use
> Bit[19:19] k_phyparam_query
> Bit[20:20] k_query_timeout
> Bit[31:21] k_preset_to_use_16g
> 

ack, thx for the clarification. I will add them in v4.

Regards,
Lorenzo

> Thanks.
> 
> > +
> > +	err = clk_bulk_enable(pcie->num_clks, pcie->clks);
> > +	if (err) {
> > +		dev_err(dev, "failed to prepare clock\n");
> > +		goto err_clk_enable;
> > +	}
> > +
> > +	return 0;
> > +
> > +err_clk_enable:
> > +	clk_bulk_unprepare(pcie->num_clks, pcie->clks);
> > +err_clk_prepare:
> > +	pm_runtime_put_sync(dev);
> > +	pm_runtime_disable(dev);
> > +	reset_control_bulk_assert(pcie->soc->phy_resets.num_resets,
> > pcie->phy_resets);
> > +err_phy_deassert:
> > +	phy_power_off(pcie->phy);
> > +err_phy_on:
> > +	phy_exit(pcie->phy);
> > +
> > +	return err;
> > +}
> > +
> >  static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie)
> >  {
> >  	struct device *dev = pcie->dev;
> > @@ -1113,8 +1196,19 @@ static const struct mtk_gen3_pcie_pdata
> > mtk_pcie_soc_mt8192 = {
> >  	},
> >  };
> >  
> > +static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_en7581 = {
> > +	.power_up = mtk_pcie_en7581_power_up,
> > +	.phy_resets = {
> > +		.id[0] = "phy-lane0",
> > +		.id[1] = "phy-lane1",
> > +		.id[2] = "phy-lane2",
> > +		.num_resets = 3,
> > +	},
> > +};
> > +
> >  static const struct of_device_id mtk_pcie_of_match[] = {
> >  	{ .compatible = "mediatek,mt8192-pcie", .data =
> > &mtk_pcie_soc_mt8192 },
> > +	{ .compatible = "airoha,en7581-pcie", .data =
> > &mtk_pcie_soc_en7581 },
> >  	{},
> >  };
> >  MODULE_DEVICE_TABLE(of, mtk_pcie_of_match);
> > -- 
> > 2.45.2
> > 

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