[PATCH v4 0/6] Add CPSW2G and CPSW9G nodes for J784S4

[PATCH v4 0/6] Add CPSW2G and CPSW9G nodes for J784S4

[Chintan Vankar]

This series adds device-tree nodes for CPSW2G and CPSW9G instance
of the CPSW Ethernet Switch on TI's J784S4 SoC. Additionally,
two device-tree overlays are also added:
1. QSGMII mode with the CPSW9G instance via the ENET EXPANSION 1
   connector.
2. USXGMII mode with MAC Ports 1 and 2 of the CPSW9G instance via
   ENET EXPANSION 1 and 2 connectors, configured in fixed-link
   mode of operation at 5Gbps link speed.

Similar to Andrew Davis patch at:
https://lore.kernel.org/r/20231117222930.228688-5-afd@ti.com/ for J721E,
similar changes are also required for J784S4 to remove dependency on the
parent node being a syscon node.

This series combines the v1 series at:
https://lore.kernel.org/r/20230522092201.127598-1-s-vadapalli@ti.com/
and the patch for Main CPSW2G node that is present in [PATCH v6 2/5] at:
https://lore.kernel.org/r/20230721132029.123881-1-j-choudhary@ti.com/
but dropped in it's next version at:
https://lore.kernel.org/r/20231019054022.175163-1-j-choudhary@ti.com/

Link to v3: https://lore.kernel.org/r/20240125100501.4137977-1-c-vankar@ti.com/

Changes from v3 to v4:
1. Add alias for MCU CPSW2G node.
2. Add alias for Main CPSW2G node.
3. Add "ti,mac-only" property for CPSW9G node.

Chintan Vankar (2):
  arm64: dts: ti: k3-j784s4-main: Fix mux-reg-masks in serdes_ln_ctrl
  arm64: dts: ti: k3-j784s4: Add alias to MCU CPSW2G

Siddharth Vadapalli (4):
  arm64: dts: ti: k3-j784s4-main: Add CPSW2G and CPSW9G nodes
  arm64: dts: ti: k3-j784s4: Add Main CPSW2G node
  arm64: dts: ti: k3-j784s4: Add overlay to enable QSGMII mode with
    CPSW9G
  arm64: dts: ti: k3-j784s4: Add overlay for dual port USXGMII mode

 arch/arm64/boot/dts/ti/Makefile               |  11 +-
 .../ti/k3-j784s4-evm-quad-port-eth-exp1.dtso  | 147 +++++++++++++
 .../ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso   |  81 +++++++
 arch/arm64/boot/dts/ti/k3-j784s4-evm.dts      |  50 +++++
 arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi    | 198 +++++++++++++++++-
 5 files changed, 480 insertions(+), 7 deletions(-)
 create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso
 create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso

-- 
2.34.1

[PATCH v4 1/6] arm64: dts: ti: k3-j784s4-main: Fix mux-reg-masks in serdes_ln_ctrl

[Chintan Vankar]

Change offset in mux-reg-masks property for serdes_ln_ctrl node
since reg-mux property is used in compatible.

Fixes: 2765149273f4 ("mux: mmio: use reg property when parent device is not a syscon")
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
Acked-by: Andrew Davis <afd@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index f2b720ed1e4f..56c8eaad6324 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -52,12 +52,12 @@ serdes_ln_ctrl: mux-controller@4080 {
 			compatible = "reg-mux";
 			reg = <0x00004080 0x30>;
 			#mux-control-cells = <1>;
-			mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
-					<0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */
-					<0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
-					<0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */
-					<0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
-					<0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */
+			mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
+					<0x8 0x3>, <0xc 0x3>, /* SERDES0 lane2/3 select */
+					<0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */
+					<0x18 0x3>, <0x1c 0x3>, /* SERDES1 lane2/3 select */
+					<0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */
+					<0x28 0x3>, <0x2c 0x3>; /* SERDES2 lane2/3 select */
 			idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>,
 				      <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
 				      <J784S4_SERDES0_LANE2_IP3_UNUSED>,
-- 
2.34.1

[PATCH v4 2/6] arm64: dts: ti: k3-j784s4: Add alias to MCU CPSW2G

[Chintan Vankar]

Add alias for the MCU CPSW2G port to enable Linux to fetch MAC Address
for the port directly from U-Boot.
---
 arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index f34b92acc56d..b74f7d3025de 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -27,6 +27,7 @@ aliases {
 		mmc1 = &main_sdhci1;
 		i2c0 = &wkup_i2c0;
 		i2c3 = &main_i2c0;
+		ethernet0 = &mcu_cpsw_port1;
 	};
 
 	memory@80000000 {
-- 
2.34.1

Re: [PATCH v4 2/6] arm64: dts: ti: k3-j784s4: Add alias to MCU CPSW2G

[Andrew Davis]

On 1/31/24 4:14 AM, Chintan Vankar wrote:
> Add alias for the MCU CPSW2G port to enable Linux to fetch MAC Address
> for the port directly from U-Boot.

Could you explain *how* this alias allows Linux to fetch a MAC
address from U-Boot? Sounds like we are doing something hacky here..

Why can't Linux fetch the MAC from efuses the same way U-Boot does,
what happens if I don't use U-Boot to boot?

Andrew

> ---
>   arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> index f34b92acc56d..b74f7d3025de 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> @@ -27,6 +27,7 @@ aliases {
>   		mmc1 = &main_sdhci1;
>   		i2c0 = &wkup_i2c0;
>   		i2c3 = &main_i2c0;
> +		ethernet0 = &mcu_cpsw_port1;
>   	};
>   
>   	memory@80000000 {

Re: [PATCH v4 2/6] arm64: dts: ti: k3-j784s4: Add alias to MCU CPSW2G

[Chintan Vankar]

On 31/01/24 21:06, Andrew Davis wrote:
> On 1/31/24 4:14 AM, Chintan Vankar wrote:
>> Add alias for the MCU CPSW2G port to enable Linux to fetch MAC Address
>> for the port directly from U-Boot.
> 
> Could you explain *how* this alias allows Linux to fetch a MAC
> address from U-Boot? Sounds like we are doing something hacky here..
> 
Using "probe_daughtercards()" function U-Boot parses MAC addresses from
EEPROM, then it internally calls "eth_env_set_enetaddr_by_index()"
function which stores these MAC addresses into environment variables
ethaddr, eth1addr, eth2addr and so on based on number of ports.

U-Boot loads DTB during boot process, and it calls
"fdt_fixup_ethernet()" function, which uses environment variables to
update MAC addresses of ethernet ports as specified in the aliases
section.

> Why can't Linux fetch the MAC from efuses the same way U-Boot does,

Linux can fetch the MAC address from efuses if "ti,syscon-efuse"
property is enabled.

> what happens if I don't use U-Boot to boot?

If you don't use U-Boot to boot then the equivalent of
"probe_daughtercards()" has to be implemented which is currently
missing.

> 
> Andrew
> 
>> ---
>>   arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts 
>> b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
>> index f34b92acc56d..b74f7d3025de 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
>> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
>> @@ -27,6 +27,7 @@ aliases {
>>           mmc1 = &main_sdhci1;
>>           i2c0 = &wkup_i2c0;
>>           i2c3 = &main_i2c0;
>> +        ethernet0 = &mcu_cpsw_port1;
>>       };
>>       memory@80000000 {

Re: [PATCH v4 2/6] arm64: dts: ti: k3-j784s4: Add alias to MCU CPSW2G

[Andrew Davis]

On 3/11/24 5:44 AM, Chintan Vankar wrote:
> 
> 
> On 31/01/24 21:06, Andrew Davis wrote:
>> On 1/31/24 4:14 AM, Chintan Vankar wrote:
>>> Add alias for the MCU CPSW2G port to enable Linux to fetch MAC Address
>>> for the port directly from U-Boot.
>>
>> Could you explain *how* this alias allows Linux to fetch a MAC
>> address from U-Boot? Sounds like we are doing something hacky here..
>>
> Using "probe_daughtercards()" function U-Boot parses MAC addresses from
> EEPROM, then it internally calls "eth_env_set_enetaddr_by_index()"
> function which stores these MAC addresses into environment variables
> ethaddr, eth1addr, eth2addr and so on based on number of ports.
> 
> U-Boot loads DTB during boot process, and it calls
> "fdt_fixup_ethernet()" function, which uses environment variables to
> update MAC addresses of ethernet ports as specified in the aliases
> section.
> 

So maybe a better question would by why does it need to use aliases
for this?

>> Why can't Linux fetch the MAC from efuses the same way U-Boot does,
> 
> Linux can fetch the MAC address from efuses if "ti,syscon-efuse"
> property is enabled.
> 

Then let's do it this way always.

>> what happens if I don't use U-Boot to boot?
> 
> If you don't use U-Boot to boot then the equivalent of
> "probe_daughtercards()" has to be implemented which is currently
> missing.
> 

Or we just let Linux fetch it instead of implementing that function
in all the possible bootloaders. This would also remove a DTB fixup.
Those fixups should be avoided if at all possible.

Andrew

>>
>> Andrew
>>
>>> ---
>>>   arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 1 +
>>>   1 file changed, 1 insertion(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
>>> index f34b92acc56d..b74f7d3025de 100644
>>> --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
>>> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
>>> @@ -27,6 +27,7 @@ aliases {
>>>           mmc1 = &main_sdhci1;
>>>           i2c0 = &wkup_i2c0;
>>>           i2c3 = &main_i2c0;
>>> +        ethernet0 = &mcu_cpsw_port1;
>>>       };
>>>       memory@80000000 {

Re: [PATCH v4 2/6] arm64: dts: ti: k3-j784s4: Add alias to MCU CPSW2G

[Chintan Vankar]

On 19/03/24 21:05, Andrew Davis wrote:
> On 3/11/24 5:44 AM, Chintan Vankar wrote:
>>
>>
>> On 31/01/24 21:06, Andrew Davis wrote:
>>> On 1/31/24 4:14 AM, Chintan Vankar wrote:
>>>> Add alias for the MCU CPSW2G port to enable Linux to fetch MAC Address
>>>> for the port directly from U-Boot.
>>>
>>> Could you explain *how* this alias allows Linux to fetch a MAC
>>> address from U-Boot? Sounds like we are doing something hacky here..
>>>
>> Using "probe_daughtercards()" function U-Boot parses MAC addresses from
>> EEPROM, then it internally calls "eth_env_set_enetaddr_by_index()"
>> function which stores these MAC addresses into environment variables
>> ethaddr, eth1addr, eth2addr and so on based on number of ports.
>>
>> U-Boot loads DTB during boot process, and it calls
>> "fdt_fixup_ethernet()" function, which uses environment variables to
>> update MAC addresses of ethernet ports as specified in the aliases
>> section.
>>
> 
> So maybe a better question would by why does it need to use aliases
> for this?
> 

Since "probe_daughtercards()" in U-Boot is implemented in a way that
it gets the MAC addresses fromm EEPROM and "fdt_fixup_ethernet()"
function configures MAC addresses for the ethernet ports as specified
in aliases section.

>>> Why can't Linux fetch the MAC from efuses the same way U-Boot does,
>>
>> Linux can fetch the MAC address from efuses if "ti,syscon-efuse"
>> property is enabled.
>>
> 
> Then let's do it this way always.
> 
Yes, Linux reads MAC addresses from efuse this way only, but the
functionality of Linux getting the MAC addresses from EEPROM is
not implemented.

>>> what happens if I don't use U-Boot to boot?
>>
>> If you don't use U-Boot to boot then the equivalent of
>> "probe_daughtercards()" has to be implemented which is currently
>> missing.
>>
> 
> Or we just let Linux fetch it instead of implementing that function
> in all the possible bootloaders. This would also remove a DTB fixup.
> Those fixups should be avoided if at all possible.
> 

Yes, we can let Linux fetch MAC addresses, but right now the Ethernet
driver in Linux can only fetch MAC addresses from "EFUSE" and not from
"EEPROM", and since the functionality to fetch MAC addresses from
"EEPROM" is implemented in U-Boot we are utilizing it.

> Andrew
> 
>>>
>>> Andrew
>>>
>>>> ---
>>>>   arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 1 +
>>>>   1 file changed, 1 insertion(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts 
>>>> b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
>>>> index f34b92acc56d..b74f7d3025de 100644
>>>> --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
>>>> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
>>>> @@ -27,6 +27,7 @@ aliases {
>>>>           mmc1 = &main_sdhci1;
>>>>           i2c0 = &wkup_i2c0;
>>>>           i2c3 = &main_i2c0;
>>>> +        ethernet0 = &mcu_cpsw_port1;
>>>>       };
>>>>       memory@80000000 {

[PATCH v4 3/6] arm64: dts: ti: k3-j784s4-main: Add CPSW2G and CPSW9G nodes

[Chintan Vankar]

From: Siddharth Vadapalli <s-vadapalli@ti.com>

J784S4 SoC has a 9 port Ethernet Switch instance with 8 external
ports and 1 host port, referred to as CPSW9G.

Add device-tree nodes for CPSW9G and disable it by default.
Device-tree overlays will be used to enable it.

Add device-tree nodes for Main CPSW2G nodes and disable it
by default.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 186 +++++++++++++++++++++
 1 file changed, 186 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index 56c8eaad6324..437a9cc94701 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -47,6 +47,19 @@ scm_conf: bus@100000 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges = <0x00 0x00 0x00100000 0x1c000>;
+		
+		cpsw1_phy_gmii_sel: phy@4034 {
+			compatible = "ti,am654-phy-gmii-sel";
+			reg = <0x4034 0x4>;
+			#phy-cells = <1>;
+		};
+
+		cpsw0_phy_gmii_sel: phy@4044 {
+			compatible = "ti,j784s4-cpsw9g-phy-gmii-sel";
+			ti,qsgmii-main-ports = <7>, <7>;
+			reg = <0x4044 0x20>;
+			#phy-cells = <1>;
+		};
 
 		serdes_ln_ctrl: mux-controller@4080 {
 			compatible = "reg-mux";
@@ -1242,6 +1255,179 @@ cpts@310d0000 {
 		};
 	};
 
+	main_cpsw0: ethernet@c000000 {
+		compatible = "ti,j784s4-cpswxg-nuss";
+		reg = <0x00 0xc000000 0x00 0x200000>;
+		reg-names = "cpsw_nuss";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>;
+		dma-coherent;
+		clocks = <&k3_clks 64 0>;
+		clock-names = "fck";
+		power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
+
+		dmas = <&main_udmap 0xca00>,
+		       <&main_udmap 0xca01>,
+		       <&main_udmap 0xca02>,
+		       <&main_udmap 0xca03>,
+		       <&main_udmap 0xca04>,
+		       <&main_udmap 0xca05>,
+		       <&main_udmap 0xca06>,
+		       <&main_udmap 0xca07>,
+		       <&main_udmap 0x4a00>;
+		dma-names = "tx0", "tx1", "tx2", "tx3",
+			    "tx4", "tx5", "tx6", "tx7",
+			    "rx";
+
+		status = "disabled";
+
+		ethernet-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			main_cpsw0_port1: port@1 {
+				reg = <1>;
+				label = "port1";
+				ti,mac-only;
+				status = "disabled";
+			};
+
+			main_cpsw0_port2: port@2 {
+				reg = <2>;
+				label = "port2";
+				ti,mac-only;
+				status = "disabled";
+			};
+
+			main_cpsw0_port3: port@3 {
+				reg = <3>;
+				label = "port3";
+				ti,mac-only;
+				status = "disabled";
+			};
+
+			main_cpsw0_port4: port@4 {
+				reg = <4>;
+				label = "port4";
+				ti,mac-only;
+				status = "disabled";
+			};
+
+			main_cpsw0_port5: port@5 {
+				reg = <5>;
+				label = "port5";
+				ti,mac-only;
+				status = "disabled";
+			};
+
+			main_cpsw0_port6: port@6 {
+				reg = <6>;
+				label = "port6";
+				ti,mac-only;
+				status = "disabled";
+			};
+
+			main_cpsw0_port7: port@7 {
+				reg = <7>;
+				label = "port7";
+				ti,mac-only;
+				status = "disabled";
+			};
+
+			main_cpsw0_port8: port@8 {
+				reg = <8>;
+				label = "port8";
+				ti,mac-only;
+				status = "disabled";
+			};
+		};
+
+		main_cpsw0_mdio: mdio@f00 {
+			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+			reg = <0x00 0xf00 0x00 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&k3_clks 64 0>;
+			clock-names = "fck";
+			bus_freq = <1000000>;
+			status = "disabled";
+		};
+
+		cpts@3d000 {
+			compatible = "ti,am65-cpts";
+			reg = <0x00 0x3d000 0x00 0x400>;
+			clocks = <&k3_clks 64 3>;
+			clock-names = "cpts";
+			interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "cpts";
+			ti,cpts-ext-ts-inputs = <4>;
+			ti,cpts-periodic-outputs = <2>;
+		};
+	};
+
+	main_cpsw1: ethernet@c200000 {
+		compatible = "ti,j721e-cpsw-nuss";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		reg = <0x00 0xc200000 0x00 0x200000>;
+		reg-names = "cpsw_nuss";
+		ranges = <0x00 0x00 0x00 0xc200000 0x00 0x200000>;
+		dma-coherent;
+		clocks = <&k3_clks 62 0>;
+		clock-names = "fck";
+		power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
+
+		dmas = <&main_udmap 0xc640>,
+			<&main_udmap 0xc641>,
+			<&main_udmap 0xc642>,
+			<&main_udmap 0xc643>,
+			<&main_udmap 0xc644>,
+			<&main_udmap 0xc645>,
+			<&main_udmap 0xc646>,
+			<&main_udmap 0xc647>,
+			<&main_udmap 0x4640>;
+		dma-names = "tx0", "tx1", "tx2", "tx3",
+				"tx4", "tx5", "tx6", "tx7",
+				"rx";
+
+		status = "disabled";
+
+		ethernet-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			main_cpsw1_port1: port@1 {
+				reg = <1>;
+				label = "port1";
+				phys = <&cpsw1_phy_gmii_sel 1>;
+				ti,mac-only;
+				status = "disabled";
+			};
+		};
+
+		main_cpsw1_mdio: mdio@f00 {
+			compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
+			reg = <0x00 0xf00 0x00 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&k3_clks 62 0>;
+			clock-names = "fck";
+			bus_freq = <1000000>;
+		};
+
+		cpts@3d000 {
+			compatible = "ti,am65-cpts";
+			reg = <0x00 0x3d000 0x00 0x400>;
+			clocks = <&k3_clks 62 3>;
+			clock-names = "cpts";
+			interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "cpts";
+			ti,cpts-ext-ts-inputs = <4>;
+			ti,cpts-periodic-outputs = <2>;
+		};
+	};
+
 	main_mcan0: can@2701000 {
 		compatible = "bosch,m_can";
 		reg = <0x00 0x02701000 0x00 0x200>,
-- 
2.34.1

[PATCH v4 4/6] arm64: dts: ti: k3-j784s4: Add Main CPSW2G node

[Chintan Vankar]

From: Siddharth Vadapalli <s-vadapalli@ti.com>

Add the device-tree nodes for the Main CPSW2G instance and enable it.

Add alias for the Main CPSW2G port to enable Linux to fetch MAC Address
for the port directly from U-Boot.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 49 ++++++++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index b74f7d3025de..be028c246c67 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -28,6 +28,7 @@ aliases {
 		i2c0 = &wkup_i2c0;
 		i2c3 = &main_i2c0;
 		ethernet0 = &mcu_cpsw_port1;
+		ethernet1 = &main_cpsw1_port1;
 	};
 
 	memory@80000000 {
@@ -280,6 +281,30 @@ &wkup_gpio0 {
 
 &main_pmx0 {
 	bootph-all;
+	main_cpsw2g_default_pins: main-cpsw2g-default-pins {
+		pinctrl-single,pins = <
+			J784S4_IOPAD(0x0b8, PIN_INPUT, 6) /* (AC34) MCASP1_ACLKX.RGMII1_RD0 */
+			J784S4_IOPAD(0x0a0, PIN_INPUT, 6) /* (AD34) MCASP0_AXR12.RGMII1_RD1 */
+			J784S4_IOPAD(0x0a4, PIN_INPUT, 6) /* (AJ36) MCASP0_AXR13.RGMII1_RD2 */
+			J784S4_IOPAD(0x0a8, PIN_INPUT, 6) /* (AF34) MCASP0_AXR14.RGMII1_RD3 */
+			J784S4_IOPAD(0x0b0, PIN_INPUT, 6) /* (AL33) MCASP1_AXR3.RGMII1_RXC */
+			J784S4_IOPAD(0x0ac, PIN_INPUT, 6) /* (AE34) MCASP0_AXR15.RGMII1_RX_CTL */
+			J784S4_IOPAD(0x08c, PIN_INPUT, 6) /* (AE35) MCASP0_AXR7.RGMII1_TD0 */
+			J784S4_IOPAD(0x090, PIN_INPUT, 6) /* (AC35) MCASP0_AXR8.RGMII1_TD1 */
+			J784S4_IOPAD(0x094, PIN_INPUT, 6) /* (AG35) MCASP0_AXR9.RGMII1_TD2 */
+			J784S4_IOPAD(0x098, PIN_INPUT, 6) /* (AH36) MCASP0_AXR10.RGMII1_TD3 */
+			J784S4_IOPAD(0x0b4, PIN_INPUT, 6) /* (AL34) MCASP1_AXR4.RGMII1_TXC */
+			J784S4_IOPAD(0x09c, PIN_INPUT, 6) /* (AF35) MCASP0_AXR11.RGMII1_TX_CTL */
+		>;
+	};
+
+	main_cpsw2g_mdio_default_pins: main-cpsw2g-mdio-default-pins {
+		pinctrl-single,pins = <
+			J784S4_IOPAD(0x0c0, PIN_INPUT, 6) /* (AD38) MCASP1_AXR0.MDIO0_MDC */
+			J784S4_IOPAD(0x0bc, PIN_INPUT, 6) /* (AD33) MCASP1_AFSX.MDIO0_MDIO */
+		>;
+	};
+	
 	main_uart8_pins_default: main-uart8-default-pins {
 		bootph-all;
 		pinctrl-single,pins = <
@@ -809,6 +834,30 @@ &mcu_cpsw_port1 {
 	phy-handle = <&mcu_phy0>;
 };
 
+&main_cpsw1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_cpsw2g_default_pins>;
+};
+
+&main_cpsw1_mdio {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_cpsw2g_mdio_default_pins>;
+
+	main_cpsw1_phy0: ethernet-phy@0 {
+		reg = <0>;
+		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+		ti,min-output-impedance;
+	};
+};
+
+&main_cpsw1_port1 {
+	status = "okay";
+	phy-mode = "rgmii-rxid";
+	phy-handle = <&main_cpsw1_phy0>;
+};
+
 &mailbox0_cluster0 {
 	status = "okay";
 	interrupts = <436>;
-- 
2.34.1

Re: [PATCH v4 4/6] arm64: dts: ti: k3-j784s4: Add Main CPSW2G node

[Andrew Davis]

On 1/31/24 4:14 AM, Chintan Vankar wrote:
> From: Siddharth Vadapalli <s-vadapalli@ti.com>
> 
> Add the device-tree nodes for the Main CPSW2G instance and enable it.
> 
> Add alias for the Main CPSW2G port to enable Linux to fetch MAC Address
> for the port directly from U-Boot.
> 
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
> Signed-off-by: Chintan Vankar <c-vankar@ti.com>
> ---
>   arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 49 ++++++++++++++++++++++++
>   1 file changed, 49 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> index b74f7d3025de..be028c246c67 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> @@ -28,6 +28,7 @@ aliases {
>   		i2c0 = &wkup_i2c0;
>   		i2c3 = &main_i2c0;
>   		ethernet0 = &mcu_cpsw_port1;
> +		ethernet1 = &main_cpsw1_port1;
>   	};
>   
>   	memory@80000000 {
> @@ -280,6 +281,30 @@ &wkup_gpio0 {
>   
>   &main_pmx0 {
>   	bootph-all;
> +	main_cpsw2g_default_pins: main-cpsw2g-default-pins {
> +		pinctrl-single,pins = <
> +			J784S4_IOPAD(0x0b8, PIN_INPUT, 6) /* (AC34) MCASP1_ACLKX.RGMII1_RD0 */
> +			J784S4_IOPAD(0x0a0, PIN_INPUT, 6) /* (AD34) MCASP0_AXR12.RGMII1_RD1 */
> +			J784S4_IOPAD(0x0a4, PIN_INPUT, 6) /* (AJ36) MCASP0_AXR13.RGMII1_RD2 */
> +			J784S4_IOPAD(0x0a8, PIN_INPUT, 6) /* (AF34) MCASP0_AXR14.RGMII1_RD3 */
> +			J784S4_IOPAD(0x0b0, PIN_INPUT, 6) /* (AL33) MCASP1_AXR3.RGMII1_RXC */
> +			J784S4_IOPAD(0x0ac, PIN_INPUT, 6) /* (AE34) MCASP0_AXR15.RGMII1_RX_CTL */
> +			J784S4_IOPAD(0x08c, PIN_INPUT, 6) /* (AE35) MCASP0_AXR7.RGMII1_TD0 */
> +			J784S4_IOPAD(0x090, PIN_INPUT, 6) /* (AC35) MCASP0_AXR8.RGMII1_TD1 */
> +			J784S4_IOPAD(0x094, PIN_INPUT, 6) /* (AG35) MCASP0_AXR9.RGMII1_TD2 */
> +			J784S4_IOPAD(0x098, PIN_INPUT, 6) /* (AH36) MCASP0_AXR10.RGMII1_TD3 */
> +			J784S4_IOPAD(0x0b4, PIN_INPUT, 6) /* (AL34) MCASP1_AXR4.RGMII1_TXC */
> +			J784S4_IOPAD(0x09c, PIN_INPUT, 6) /* (AF35) MCASP0_AXR11.RGMII1_TX_CTL */
> +		>;
> +	};
> +
> +	main_cpsw2g_mdio_default_pins: main-cpsw2g-mdio-default-pins {
> +		pinctrl-single,pins = <
> +			J784S4_IOPAD(0x0c0, PIN_INPUT, 6) /* (AD38) MCASP1_AXR0.MDIO0_MDC */
> +			J784S4_IOPAD(0x0bc, PIN_INPUT, 6) /* (AD33) MCASP1_AFSX.MDIO0_MDIO */
> +		>;
> +	};
> +	
>   	main_uart8_pins_default: main-uart8-default-pins {
>   		bootph-all;
>   		pinctrl-single,pins = <
> @@ -809,6 +834,30 @@ &mcu_cpsw_port1 {
>   	phy-handle = <&mcu_phy0>;
>   };
>   
> +&main_cpsw1 {
> +	status = "okay";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&main_cpsw2g_default_pins>;
> +};
> +
> +&main_cpsw1_mdio {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&main_cpsw2g_mdio_default_pins>;

If we need this pinmux info, why wasn't this node disabled? You disabled
the main_cpsw0_mdio instance, but not this one. Disable this by default
in the patch before this, then status = "okay" it here.

Andrew

> +
> +	main_cpsw1_phy0: ethernet-phy@0 {
> +		reg = <0>;
> +		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> +		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> +		ti,min-output-impedance;
> +	};
> +};
> +
> +&main_cpsw1_port1 {
> +	status = "okay";
> +	phy-mode = "rgmii-rxid";
> +	phy-handle = <&main_cpsw1_phy0>;
> +};
> +
>   &mailbox0_cluster0 {
>   	status = "okay";
>   	interrupts = <436>;

[PATCH v4 5/6] arm64: dts: ti: k3-j784s4: Add overlay to enable QSGMII mode with CPSW9G

[Chintan Vankar]

From: Siddharth Vadapalli <s-vadapalli@ti.com>

The J7 Quad Port Add-On Ethernet Card for J784S4 EVM supports
QSGMII mode. Use the overlay to configure CPSW9G ports in QSGMII
mode with the Add-On Ethernet Card connected to the ENET Expansion
1 slot on the EVM.

Add support to reset the PHY from kernel by using gpio-hog and
gpio-reset.

Add aliases for CPSW9G ports to enable kernel to fetch MAC Addresses
directly from U-Boot.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---
 arch/arm64/boot/dts/ti/Makefile               |   7 +-
 .../ti/k3-j784s4-evm-quad-port-eth-exp1.dtso  | 147 ++++++++++++++++++
 2 files changed, 153 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso

diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 52c1dc910308..836bc197d932 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -81,6 +81,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-pcie1-ep.dtbo
 # Boards with J784s4 SoC
 dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-quad-port-eth-exp1.dtbo
 
 # Build time test only, enabled by CONFIG_OF_ALL_DTBS
 k3-am625-beagleplay-csi2-ov5640-dtbs := k3-am625-beagleplay.dtb \
@@ -109,6 +110,8 @@ k3-j721e-evm-pcie0-ep-dtbs := k3-j721e-common-proc-board.dtb \
 	k3-j721e-evm-pcie0-ep.dtbo
 k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \
 	k3-j721s2-evm-pcie1-ep.dtbo
+k3-j784s4-evm-quad-port-eth-exp1-dtbs := k3-j784s4-evm.dtb \
+	k3-j784s4-evm-quad-port-eth-exp1.dtbo
 dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
 	k3-am625-beagleplay-csi2-tevi-ov5640.dtb \
 	k3-am625-sk-csi2-imx219.dtb \
@@ -121,7 +124,8 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
 	k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \
 	k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \
 	k3-j721e-evm-pcie0-ep.dtb \
-	k3-j721s2-evm-pcie1-ep.dtb
+	k3-j721s2-evm-pcie1-ep.dtb \
+	k3-j784s4-evm-quad-port-eth-exp1.dtb
 
 # Enable support for device-tree overlays
 DTC_FLAGS_k3-am625-beagleplay += -@
@@ -132,3 +136,4 @@ DTC_FLAGS_k3-am642-tqma64xxl-mbax4xxl += -@
 DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@
 DTC_FLAGS_k3-j721e-common-proc-board += -@
 DTC_FLAGS_k3-j721s2-common-proc-board += -@
+DTC_FLAGS_k3-j784s4-evm += -@
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso b/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso
new file mode 100644
index 000000000000..0667389b07be
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+/**
+ * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
+ * J784S4 EVM. The Add-On Ethernet Card has to be connected to ENET Expansion 1 slot on the
+ * board.
+ *
+ * Product Datasheet: https://www.ti.com/lit/ug/spruj74/spruj74.pdf
+ *
+ * Link to QSGMII Daughtercard: https://www.ti.com/tool/J721EXENETXPANEVM
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy.h>
+
+#include "k3-pinctrl.h"
+#include "k3-serdes.h"
+
+&{/} {
+	aliases {
+		ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@5";
+		ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@6";
+		ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@7";
+		ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@8";
+		ethernet5 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1";
+	};
+};
+
+&main_cpsw0 {
+	status = "okay";
+};
+
+&main_cpsw0_port5 {
+	status = "okay";
+	phy-handle = <&cpsw9g_phy1>;
+	phy-mode = "qsgmii";
+	mac-address = [00 00 00 00 00 00];
+	phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_qsgmii_link>;
+	phy-names = "mac", "serdes";
+};
+
+&main_cpsw0_port6 {
+	status = "okay";
+	phy-handle = <&cpsw9g_phy2>;
+	phy-mode = "qsgmii";
+	mac-address = [00 00 00 00 00 00];
+	phys = <&cpsw0_phy_gmii_sel 6>, <&serdes2_qsgmii_link>;
+	phy-names = "mac", "serdes";
+};
+
+&main_cpsw0_port7 {
+	status = "okay";
+	phy-handle = <&cpsw9g_phy0>;
+	phy-mode = "qsgmii";
+	mac-address = [00 00 00 00 00 00];
+	phys = <&cpsw0_phy_gmii_sel 7>, <&serdes2_qsgmii_link>;
+	phy-names = "mac", "serdes";
+};
+
+&main_cpsw0_port8 {
+	status = "okay";
+	phy-handle = <&cpsw9g_phy3>;
+	phy-mode = "qsgmii";
+	mac-address = [00 00 00 00 00 00];
+	phys = <&cpsw0_phy_gmii_sel 8>, <&serdes2_qsgmii_link>;
+	phy-names = "mac", "serdes";
+};
+
+&main_cpsw0_mdio {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&mdio0_default_pins>;
+	bus_freq = <1000000>;
+	reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>;
+	reset-post-delay-us = <120000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	cpsw9g_phy0: ethernet-phy@16 {
+		reg = <16>;
+	};
+	cpsw9g_phy1: ethernet-phy@17 {
+		reg = <17>;
+	};
+	cpsw9g_phy2: ethernet-phy@18 {
+		reg = <18>;
+	};
+	cpsw9g_phy3: ethernet-phy@19 {
+		reg = <19>;
+	};
+};
+
+&exp2 {
+	/* Power-up ENET1 EXPANDER PHY. */
+	qsgmii-line-hog {
+		gpio-hog;
+		gpios = <16 GPIO_ACTIVE_HIGH>;
+		output-low;
+	};
+
+	/* Toggle MUX2 for MDIO lines */
+	mux-sel-hog {
+		gpio-hog;
+		gpios = <13 GPIO_ACTIVE_HIGH>, <14 GPIO_ACTIVE_HIGH>, <15 GPIO_ACTIVE_HIGH>;
+		output-high;
+	};
+};
+
+&main_pmx0 {
+	mdio0_default_pins: mdio0-default-pins {
+		pinctrl-single,pins = <
+			J784S4_IOPAD(0x05c, PIN_INPUT, 4) /* (AC36) MCASP2_AXR0.MDIO1_MDIO */
+			J784S4_IOPAD(0x058, PIN_INPUT, 4) /* (AE37) MCASP2_AFSX.MDIO1_MDC */
+		>;
+	};
+};
+
+&serdes_ln_ctrl {
+	idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
+		      <J784S4_SERDES0_LANE2_IP3_UNUSED>, <J784S4_SERDES0_LANE3_USB>,
+		      <J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
+		      <J784S4_SERDES1_LANE2_PCIE0_LANE2>, <J784S4_SERDES1_LANE3_PCIE0_LANE3>,
+		      <J784S4_SERDES2_LANE0_QSGMII_LANE5>, <J784S4_SERDES2_LANE1_QSGMII_LANE6>,
+		      <J784S4_SERDES2_LANE2_QSGMII_LANE7>, <J784S4_SERDES2_LANE3_QSGMII_LANE8>;
+};
+
+&serdes_wiz2 {
+	status = "okay";
+};
+
+&serdes2 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	serdes2_qsgmii_link: phy@0 {
+		reg = <2>;
+		cdns,num-lanes = <1>;
+		#phy-cells = <0>;
+		cdns,phy-type = <PHY_TYPE_QSGMII>;
+		resets = <&serdes_wiz2 3>;
+	};
+};
-- 
2.34.1

Re: [PATCH v4 5/6] arm64: dts: ti: k3-j784s4: Add overlay to enable QSGMII mode with CPSW9G

[Andrew Davis]

On 1/31/24 4:14 AM, Chintan Vankar wrote:
> From: Siddharth Vadapalli <s-vadapalli@ti.com>
> 
> The J7 Quad Port Add-On Ethernet Card for J784S4 EVM supports
> QSGMII mode. Use the overlay to configure CPSW9G ports in QSGMII
> mode with the Add-On Ethernet Card connected to the ENET Expansion
> 1 slot on the EVM.
> 
> Add support to reset the PHY from kernel by using gpio-hog and
> gpio-reset.
> 
> Add aliases for CPSW9G ports to enable kernel to fetch MAC Addresses
> directly from U-Boot.
> 
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> Signed-off-by: Chintan Vankar <c-vankar@ti.com>
> ---
>   arch/arm64/boot/dts/ti/Makefile               |   7 +-
>   .../ti/k3-j784s4-evm-quad-port-eth-exp1.dtso  | 147 ++++++++++++++++++
>   2 files changed, 153 insertions(+), 1 deletion(-)
>   create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso
> 
> diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
> index 52c1dc910308..836bc197d932 100644
> --- a/arch/arm64/boot/dts/ti/Makefile
> +++ b/arch/arm64/boot/dts/ti/Makefile
> @@ -81,6 +81,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-pcie1-ep.dtbo
>   # Boards with J784s4 SoC
>   dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb
>   dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb
> +dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-quad-port-eth-exp1.dtbo
>   
>   # Build time test only, enabled by CONFIG_OF_ALL_DTBS
>   k3-am625-beagleplay-csi2-ov5640-dtbs := k3-am625-beagleplay.dtb \
> @@ -109,6 +110,8 @@ k3-j721e-evm-pcie0-ep-dtbs := k3-j721e-common-proc-board.dtb \
>   	k3-j721e-evm-pcie0-ep.dtbo
>   k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \
>   	k3-j721s2-evm-pcie1-ep.dtbo
> +k3-j784s4-evm-quad-port-eth-exp1-dtbs := k3-j784s4-evm.dtb \
> +	k3-j784s4-evm-quad-port-eth-exp1.dtbo
>   dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
>   	k3-am625-beagleplay-csi2-tevi-ov5640.dtb \
>   	k3-am625-sk-csi2-imx219.dtb \
> @@ -121,7 +124,8 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
>   	k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \
>   	k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \
>   	k3-j721e-evm-pcie0-ep.dtb \
> -	k3-j721s2-evm-pcie1-ep.dtb
> +	k3-j721s2-evm-pcie1-ep.dtb \
> +	k3-j784s4-evm-quad-port-eth-exp1.dtb
>   
>   # Enable support for device-tree overlays
>   DTC_FLAGS_k3-am625-beagleplay += -@
> @@ -132,3 +136,4 @@ DTC_FLAGS_k3-am642-tqma64xxl-mbax4xxl += -@
>   DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@
>   DTC_FLAGS_k3-j721e-common-proc-board += -@
>   DTC_FLAGS_k3-j721s2-common-proc-board += -@
> +DTC_FLAGS_k3-j784s4-evm += -@
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso b/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso
> new file mode 100644
> index 000000000000..0667389b07be
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso
> @@ -0,0 +1,147 @@
> +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
> +/**
> + * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
> + * J784S4 EVM. The Add-On Ethernet Card has to be connected to ENET Expansion 1 slot on the
> + * board.
> + *
> + * Product Datasheet: https://www.ti.com/lit/ug/spruj74/spruj74.pdf
> + *
> + * Link to QSGMII Daughtercard: https://www.ti.com/tool/J721EXENETXPANEVM
> + *
> + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/phy/phy-cadence.h>
> +#include <dt-bindings/phy/phy.h>
> +
> +#include "k3-pinctrl.h"
> +#include "k3-serdes.h"
> +
> +&{/} {
> +	aliases {
> +		ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@5";

Didn't you already set ethernet1 to be main_cpsw1_port1 in the base, does this
actually behave the way you want?

Otherwise looks okay,

Reviewed-by: Andrew Davis <afd@ti.com>

> +		ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@6";
> +		ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@7";
> +		ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@8";
> +		ethernet5 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1";
> +	};
> +};
> +
> +&main_cpsw0 {
> +	status = "okay";
> +};
> +
> +&main_cpsw0_port5 {
> +	status = "okay";
> +	phy-handle = <&cpsw9g_phy1>;
> +	phy-mode = "qsgmii";
> +	mac-address = [00 00 00 00 00 00];
> +	phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_qsgmii_link>;
> +	phy-names = "mac", "serdes";
> +};
> +
> +&main_cpsw0_port6 {
> +	status = "okay";
> +	phy-handle = <&cpsw9g_phy2>;
> +	phy-mode = "qsgmii";
> +	mac-address = [00 00 00 00 00 00];
> +	phys = <&cpsw0_phy_gmii_sel 6>, <&serdes2_qsgmii_link>;
> +	phy-names = "mac", "serdes";
> +};
> +
> +&main_cpsw0_port7 {
> +	status = "okay";
> +	phy-handle = <&cpsw9g_phy0>;
> +	phy-mode = "qsgmii";
> +	mac-address = [00 00 00 00 00 00];
> +	phys = <&cpsw0_phy_gmii_sel 7>, <&serdes2_qsgmii_link>;
> +	phy-names = "mac", "serdes";
> +};
> +
> +&main_cpsw0_port8 {
> +	status = "okay";
> +	phy-handle = <&cpsw9g_phy3>;
> +	phy-mode = "qsgmii";
> +	mac-address = [00 00 00 00 00 00];
> +	phys = <&cpsw0_phy_gmii_sel 8>, <&serdes2_qsgmii_link>;
> +	phy-names = "mac", "serdes";
> +};
> +
> +&main_cpsw0_mdio {
> +	status = "okay";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&mdio0_default_pins>;
> +	bus_freq = <1000000>;
> +	reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>;
> +	reset-post-delay-us = <120000>;
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +
> +	cpsw9g_phy0: ethernet-phy@16 {
> +		reg = <16>;
> +	};
> +	cpsw9g_phy1: ethernet-phy@17 {
> +		reg = <17>;
> +	};
> +	cpsw9g_phy2: ethernet-phy@18 {
> +		reg = <18>;
> +	};
> +	cpsw9g_phy3: ethernet-phy@19 {
> +		reg = <19>;
> +	};
> +};
> +
> +&exp2 {
> +	/* Power-up ENET1 EXPANDER PHY. */
> +	qsgmii-line-hog {
> +		gpio-hog;
> +		gpios = <16 GPIO_ACTIVE_HIGH>;
> +		output-low;
> +	};
> +
> +	/* Toggle MUX2 for MDIO lines */
> +	mux-sel-hog {
> +		gpio-hog;
> +		gpios = <13 GPIO_ACTIVE_HIGH>, <14 GPIO_ACTIVE_HIGH>, <15 GPIO_ACTIVE_HIGH>;
> +		output-high;
> +	};
> +};
> +
> +&main_pmx0 {
> +	mdio0_default_pins: mdio0-default-pins {
> +		pinctrl-single,pins = <
> +			J784S4_IOPAD(0x05c, PIN_INPUT, 4) /* (AC36) MCASP2_AXR0.MDIO1_MDIO */
> +			J784S4_IOPAD(0x058, PIN_INPUT, 4) /* (AE37) MCASP2_AFSX.MDIO1_MDC */
> +		>;
> +	};
> +};
> +
> +&serdes_ln_ctrl {
> +	idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
> +		      <J784S4_SERDES0_LANE2_IP3_UNUSED>, <J784S4_SERDES0_LANE3_USB>,
> +		      <J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
> +		      <J784S4_SERDES1_LANE2_PCIE0_LANE2>, <J784S4_SERDES1_LANE3_PCIE0_LANE3>,
> +		      <J784S4_SERDES2_LANE0_QSGMII_LANE5>, <J784S4_SERDES2_LANE1_QSGMII_LANE6>,
> +		      <J784S4_SERDES2_LANE2_QSGMII_LANE7>, <J784S4_SERDES2_LANE3_QSGMII_LANE8>;
> +};
> +
> +&serdes_wiz2 {
> +	status = "okay";
> +};
> +
> +&serdes2 {
> +	status = "okay";
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	serdes2_qsgmii_link: phy@0 {
> +		reg = <2>;
> +		cdns,num-lanes = <1>;
> +		#phy-cells = <0>;
> +		cdns,phy-type = <PHY_TYPE_QSGMII>;
> +		resets = <&serdes_wiz2 3>;
> +	};
> +};

Re: [PATCH v4 5/6] arm64: dts: ti: k3-j784s4: Add overlay to enable QSGMII mode with CPSW9G

[Chintan Vankar]

On 31/01/24 21:20, Andrew Davis wrote:
> On 1/31/24 4:14 AM, Chintan Vankar wrote:
>> From: Siddharth Vadapalli <s-vadapalli@ti.com>
>>
>> The J7 Quad Port Add-On Ethernet Card for J784S4 EVM supports
>> QSGMII mode. Use the overlay to configure CPSW9G ports in QSGMII
>> mode with the Add-On Ethernet Card connected to the ENET Expansion
>> 1 slot on the EVM.
>>
>> Add support to reset the PHY from kernel by using gpio-hog and
>> gpio-reset.
>>
>> Add aliases for CPSW9G ports to enable kernel to fetch MAC Addresses
>> directly from U-Boot.
>>
>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
>> Signed-off-by: Chintan Vankar <c-vankar@ti.com>
>> ---
>>   arch/arm64/boot/dts/ti/Makefile               |   7 +-
>>   .../ti/k3-j784s4-evm-quad-port-eth-exp1.dtso  | 147 ++++++++++++++++++
>>   2 files changed, 153 insertions(+), 1 deletion(-)
>>   create mode 100644 
>> arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso
>>
>> diff --git a/arch/arm64/boot/dts/ti/Makefile 
>> b/arch/arm64/boot/dts/ti/Makefile
>> index 52c1dc910308..836bc197d932 100644
>> --- a/arch/arm64/boot/dts/ti/Makefile
>> +++ b/arch/arm64/boot/dts/ti/Makefile
>> @@ -81,6 +81,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-pcie1-ep.dtbo
>>   # Boards with J784s4 SoC
>>   dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb
>>   dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb
>> +dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-quad-port-eth-exp1.dtbo
>>   # Build time test only, enabled by CONFIG_OF_ALL_DTBS
>>   k3-am625-beagleplay-csi2-ov5640-dtbs := k3-am625-beagleplay.dtb \
>> @@ -109,6 +110,8 @@ k3-j721e-evm-pcie0-ep-dtbs := 
>> k3-j721e-common-proc-board.dtb \
>>       k3-j721e-evm-pcie0-ep.dtbo
>>   k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \
>>       k3-j721s2-evm-pcie1-ep.dtbo
>> +k3-j784s4-evm-quad-port-eth-exp1-dtbs := k3-j784s4-evm.dtb \
>> +    k3-j784s4-evm-quad-port-eth-exp1.dtbo
>>   dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
>>       k3-am625-beagleplay-csi2-tevi-ov5640.dtb \
>>       k3-am625-sk-csi2-imx219.dtb \
>> @@ -121,7 +124,8 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
>>       k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \
>>       k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \
>>       k3-j721e-evm-pcie0-ep.dtb \
>> -    k3-j721s2-evm-pcie1-ep.dtb
>> +    k3-j721s2-evm-pcie1-ep.dtb \
>> +    k3-j784s4-evm-quad-port-eth-exp1.dtb
>>   # Enable support for device-tree overlays
>>   DTC_FLAGS_k3-am625-beagleplay += -@
>> @@ -132,3 +136,4 @@ DTC_FLAGS_k3-am642-tqma64xxl-mbax4xxl += -@
>>   DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@
>>   DTC_FLAGS_k3-j721e-common-proc-board += -@
>>   DTC_FLAGS_k3-j721s2-common-proc-board += -@
>> +DTC_FLAGS_k3-j784s4-evm += -@
>> diff --git 
>> a/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso 
>> b/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso
>> new file mode 100644
>> index 000000000000..0667389b07be
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso
>> @@ -0,0 +1,147 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
>> +/**
>> + * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP 
>> Add-On Ethernet Card with
>> + * J784S4 EVM. The Add-On Ethernet Card has to be connected to ENET 
>> Expansion 1 slot on the
>> + * board.
>> + *
>> + * Product Datasheet: https://www.ti.com/lit/ug/spruj74/spruj74.pdf
>> + *
>> + * Link to QSGMII Daughtercard: 
>> https://www.ti.com/tool/J721EXENETXPANEVM
>> + *
>> + * Copyright (C) 2024 Texas Instruments Incorporated - 
>> https://www.ti.com/
>> + */
>> +
>> +/dts-v1/;
>> +/plugin/;
>> +
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/phy/phy-cadence.h>
>> +#include <dt-bindings/phy/phy.h>
>> +
>> +#include "k3-pinctrl.h"
>> +#include "k3-serdes.h"
>> +
>> +&{/} {
>> +    aliases {
>> +        ethernet1 = 
>> "/bus@100000/ethernet@c000000/ethernet-ports/port@5";
> 
> Didn't you already set ethernet1 to be main_cpsw1_port1 in the base, 
> does this
> actually behave the way you want?

Yes. It behaves the way it is configured, explanation of how it
configures MAC addresses is explained at:
https://lore.kernel.org/all/0512d57f-af22-4bd8-8266-33d943d7eb4a@ti.com/

> 
> Otherwise looks okay,
> 
> Reviewed-by: Andrew Davis <afd@ti.com>
> 
>> +        ethernet2 = 
>> "/bus@100000/ethernet@c000000/ethernet-ports/port@6";
>> +        ethernet3 = 
>> "/bus@100000/ethernet@c000000/ethernet-ports/port@7";
>> +        ethernet4 = 
>> "/bus@100000/ethernet@c000000/ethernet-ports/port@8";
>> +        ethernet5 = 
>> "/bus@100000/ethernet@c200000/ethernet-ports/port@1";
>> +    };
>> +};
>> +
>> +&main_cpsw0 {
>> +    status = "okay";
>> +};
>> +
>> +&main_cpsw0_port5 {
>> +    status = "okay";
>> +    phy-handle = <&cpsw9g_phy1>;
>> +    phy-mode = "qsgmii";
>> +    mac-address = [00 00 00 00 00 00];
>> +    phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_qsgmii_link>;
>> +    phy-names = "mac", "serdes";
>> +};
>> +
>> +&main_cpsw0_port6 {
>> +    status = "okay";
>> +    phy-handle = <&cpsw9g_phy2>;
>> +    phy-mode = "qsgmii";
>> +    mac-address = [00 00 00 00 00 00];
>> +    phys = <&cpsw0_phy_gmii_sel 6>, <&serdes2_qsgmii_link>;
>> +    phy-names = "mac", "serdes";
>> +};
>> +
>> +&main_cpsw0_port7 {
>> +    status = "okay";
>> +    phy-handle = <&cpsw9g_phy0>;
>> +    phy-mode = "qsgmii";
>> +    mac-address = [00 00 00 00 00 00];
>> +    phys = <&cpsw0_phy_gmii_sel 7>, <&serdes2_qsgmii_link>;
>> +    phy-names = "mac", "serdes";
>> +};
>> +
>> +&main_cpsw0_port8 {
>> +    status = "okay";
>> +    phy-handle = <&cpsw9g_phy3>;
>> +    phy-mode = "qsgmii";
>> +    mac-address = [00 00 00 00 00 00];
>> +    phys = <&cpsw0_phy_gmii_sel 8>, <&serdes2_qsgmii_link>;
>> +    phy-names = "mac", "serdes";
>> +};
>> +
>> +&main_cpsw0_mdio {
>> +    status = "okay";
>> +    pinctrl-names = "default";
>> +    pinctrl-0 = <&mdio0_default_pins>;
>> +    bus_freq = <1000000>;
>> +    reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>;
>> +    reset-post-delay-us = <120000>;
>> +    #address-cells = <1>;
>> +    #size-cells = <0>;
>> +
>> +    cpsw9g_phy0: ethernet-phy@16 {
>> +        reg = <16>;
>> +    };
>> +    cpsw9g_phy1: ethernet-phy@17 {
>> +        reg = <17>;
>> +    };
>> +    cpsw9g_phy2: ethernet-phy@18 {
>> +        reg = <18>;
>> +    };
>> +    cpsw9g_phy3: ethernet-phy@19 {
>> +        reg = <19>;
>> +    };
>> +};
>> +
>> +&exp2 {
>> +    /* Power-up ENET1 EXPANDER PHY. */
>> +    qsgmii-line-hog {
>> +        gpio-hog;
>> +        gpios = <16 GPIO_ACTIVE_HIGH>;
>> +        output-low;
>> +    };
>> +
>> +    /* Toggle MUX2 for MDIO lines */
>> +    mux-sel-hog {
>> +        gpio-hog;
>> +        gpios = <13 GPIO_ACTIVE_HIGH>, <14 GPIO_ACTIVE_HIGH>, <15 
>> GPIO_ACTIVE_HIGH>;
>> +        output-high;
>> +    };
>> +};
>> +
>> +&main_pmx0 {
>> +    mdio0_default_pins: mdio0-default-pins {
>> +        pinctrl-single,pins = <
>> +            J784S4_IOPAD(0x05c, PIN_INPUT, 4) /* (AC36) 
>> MCASP2_AXR0.MDIO1_MDIO */
>> +            J784S4_IOPAD(0x058, PIN_INPUT, 4) /* (AE37) 
>> MCASP2_AFSX.MDIO1_MDC */
>> +        >;
>> +    };
>> +};
>> +
>> +&serdes_ln_ctrl {
>> +    idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, 
>> <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
>> +              <J784S4_SERDES0_LANE2_IP3_UNUSED>, 
>> <J784S4_SERDES0_LANE3_USB>,
>> +              <J784S4_SERDES1_LANE0_PCIE0_LANE0>, 
>> <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
>> +              <J784S4_SERDES1_LANE2_PCIE0_LANE2>, 
>> <J784S4_SERDES1_LANE3_PCIE0_LANE3>,
>> +              <J784S4_SERDES2_LANE0_QSGMII_LANE5>, 
>> <J784S4_SERDES2_LANE1_QSGMII_LANE6>,
>> +              <J784S4_SERDES2_LANE2_QSGMII_LANE7>, 
>> <J784S4_SERDES2_LANE3_QSGMII_LANE8>;
>> +};
>> +
>> +&serdes_wiz2 {
>> +    status = "okay";
>> +};
>> +
>> +&serdes2 {
>> +    status = "okay";
>> +    #address-cells = <1>;
>> +    #size-cells = <0>;
>> +    serdes2_qsgmii_link: phy@0 {
>> +        reg = <2>;
>> +        cdns,num-lanes = <1>;
>> +        #phy-cells = <0>;
>> +        cdns,phy-type = <PHY_TYPE_QSGMII>;
>> +        resets = <&serdes_wiz2 3>;
>> +    };
>> +};

[PATCH v4 6/6] arm64: dts: ti: k3-j784s4: Add overlay for dual port USXGMII mode

[Chintan Vankar]

From: Siddharth Vadapalli <s-vadapalli@ti.com>

The CPSW9G instance of the CPSW Ethernet Switch supports USXGMII mode
with MAC Ports 1 and 2 of the instance, which are connected to ENET
Expansion 1 and ENET Expansion 2 slots on the EVM respectively, through
the Serdes2 instance of the SERDES.

Enable CPSW9G MAC Ports 1 and 2 in fixed-link configuration USXGMII mode
at 5 Gbps each.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---
 arch/arm64/boot/dts/ti/Makefile               |  6 +-
 .../ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso   | 81 +++++++++++++++++++
 2 files changed, 86 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso

diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 836bc197d932..97be325235dc 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -82,6 +82,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-pcie1-ep.dtbo
 dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-quad-port-eth-exp1.dtbo
+dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-usxgmii-exp1-exp2.dtbo
 
 # Build time test only, enabled by CONFIG_OF_ALL_DTBS
 k3-am625-beagleplay-csi2-ov5640-dtbs := k3-am625-beagleplay.dtb \
@@ -112,6 +113,8 @@ k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \
 	k3-j721s2-evm-pcie1-ep.dtbo
 k3-j784s4-evm-quad-port-eth-exp1-dtbs := k3-j784s4-evm.dtb \
 	k3-j784s4-evm-quad-port-eth-exp1.dtbo
+k3-j784s4-evm-usxgmii-exp1-exp2.dtbs := k3-j784s4-evm.dtb \
+	k3-j784s4-evm-usxgmii-exp1-exp2.dtbo
 dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
 	k3-am625-beagleplay-csi2-tevi-ov5640.dtb \
 	k3-am625-sk-csi2-imx219.dtb \
@@ -125,7 +128,8 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
 	k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \
 	k3-j721e-evm-pcie0-ep.dtb \
 	k3-j721s2-evm-pcie1-ep.dtb \
-	k3-j784s4-evm-quad-port-eth-exp1.dtb
+	k3-j784s4-evm-quad-port-eth-exp1.dtb \
+	k3-j784s4-evm-usxgmii-exp1-exp2.dtb
 
 # Enable support for device-tree overlays
 DTC_FLAGS_k3-am625-beagleplay += -@
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso b/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso
new file mode 100644
index 000000000000..b8e7fed6105a
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+/**
+ * DT Overlay for CPSW9G in dual port fixed-link USXGMII mode using ENET-1
+ * and ENET-2 Expansion slots of J784S4 EVM.
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy.h>
+
+#include "k3-serdes.h"
+
+&{/} {
+	aliases {
+		ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
+		ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
+		ethernet3 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1";
+	};
+};
+
+&main_cpsw0 {
+	status = "okay";
+	pinctrl-names = "default";
+};
+
+&main_cpsw0_port1 {
+	status = "okay";
+	phy-mode = "usxgmii";
+	mac-address = [00 00 00 00 00 00];
+	phys = <&cpsw0_phy_gmii_sel 1>, <&serdes2_usxgmii_link>;
+	phy-names = "mac", "serdes";
+	fixed-link {
+		speed = <5000>;
+		full-duplex;
+	};
+};
+
+&main_cpsw0_port2 {
+	status = "okay";
+	phy-mode = "usxgmii";
+	mac-address = [00 00 00 00 00 00];
+	phys = <&cpsw0_phy_gmii_sel 2>, <&serdes2_usxgmii_link>;
+	phy-names = "mac", "serdes";
+	fixed-link {
+		speed = <5000>;
+		full-duplex;
+	};
+};
+
+&serdes_wiz2 {
+	status = "okay";
+	assigned-clock-parents = <&k3_clks 406 9>; /* Use 156.25 MHz clock for USXGMII */
+};
+
+&serdes2 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	serdes2_usxgmii_link: phy@2 {
+		reg = <2>;
+		cdns,num-lanes = <2>;
+		#phy-cells = <0>;
+		cdns,phy-type = <PHY_TYPE_USXGMII>;
+		resets = <&serdes_wiz2 3>, <&serdes_wiz2 4>;
+	};
+};
+
+&serdes_ln_ctrl {
+	idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
+		      <J784S4_SERDES0_LANE2_IP3_UNUSED>, <J784S4_SERDES0_LANE3_USB>,
+		      <J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
+		      <J784S4_SERDES1_LANE2_PCIE0_LANE2>, <J784S4_SERDES1_LANE3_PCIE0_LANE3>,
+		      <J784S4_SERDES2_LANE0_IP2_UNUSED>, <J784S4_SERDES2_LANE1_IP2_UNUSED>,
+		      <J784S4_SERDES2_LANE2_QSGMII_LANE1>, <J784S4_SERDES2_LANE3_QSGMII_LANE2>;
+};
-- 
2.34.1