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Wed, 13 May 2026 10:02:08 -0700 (PDT) X-Received: by 2002:a17:902:f551:b0:2b0:4fb6:85ce with SMTP id d9443c01a7336-2bd30210db5mr41155195ad.21.1778691726554; Wed, 13 May 2026 10:02:06 -0700 (PDT) Received: from [192.168.0.172] ([49.205.255.126]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bc83101ee1sm141611295ad.79.2026.05.13.10.01.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 13 May 2026 10:02:06 -0700 (PDT) Message-ID: Date: Wed, 13 May 2026 22:31:55 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 12/14] media: iris: Add platform data for glymur To: Dmitry Baryshkov Cc: Vishnu Reddy , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Joerg Roedel , Will Deacon , Robin Murphy , Hans Verkuil , Stefan Schmidt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stanimir Varbanov , Jorge Ramirez-Ortiz , Del Regno , Bjorn Andersson , Konrad Dybcio , linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, iommu@lists.linux.dev, Krzysztof Kozlowski , devicetree@vger.kernel.org References: <20260509-glymur-v5-0-7fbb340c5dbd@oss.qualcomm.com> <20260509-glymur-v5-12-7fbb340c5dbd@oss.qualcomm.com> Content-Language: en-US From: Vikash Garodia In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTEzMDE3MiBTYWx0ZWRfXy8Hzgs04c4jB gEzMX/KJ75rJ4kto3iONGqFMzcp9roNXt3/1dCkjiJqxGprNO2/QznTVsfnHo3IXuSRgVxbrn4b O+WnGxaqvWhx6PTJXJG5xf0oDVbDJpW8nK+2WZXm1woy8V+YiQvdn/tj5gZt0jQI/DGXTHuS/sv 8nCTTSs20Ub3S0Pkid2SpQ5AHSrmbNnOYHdjtR2h3WHbKHvMP2rpeAB1UbnQKy4DSdQ1iDBmCKk zFOuVQjtMeWM+TMTyL0ZurENEVyyspDCg7I0dca1+G5LHuf58Wf9xfltBmlwPhxWzC0CzdZFXRz WvPDhYD7nlKNzz/6cbs6BhyjeJ4hX6nWb0JMjLtPVs2GQ8viPSlqcFZbzGewjM183bAq4VV230D tPbKYZR/tvx3FDTjTKJivjoWCGvPPw== X-Authority-Analysis: v=2.4 cv=G9Ys1dk5 c=1 sm=1 tr=0 ts=6a04ae92 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=6GFGFuPpdQFN+sW0UwB+2Q==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=BiA4-BlHbpJUGHtcRRkA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-GUID: 6A5wOOwtGLfN31GB7mSY3b_sENDF5MGh X-Proofpoint-ORIG-GUID: 6A5wOOwtGLfN31GB7mSY3b_sENDF5MGh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-13_01,2026-05-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 malwarescore=0 spamscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605050000 definitions=main-2605130172 On 5/13/2026 9:33 PM, Dmitry Baryshkov wrote: > On Wed, May 13, 2026 at 08:00:39PM +0530, Vikash Garodia wrote: >> >> >> On 5/13/2026 7:47 PM, Dmitry Baryshkov wrote: >>> On Mon, May 11, 2026 at 09:45:01PM +0530, Vishnu Reddy wrote: >>>> >>>> On 5/9/2026 2:35 AM, Dmitry Baryshkov wrote: >>>>> On Sat, May 09, 2026 at 12:30:01AM +0530, Vishnu Reddy wrote: >>>>>> On glymur platform, the iris core shares most properties with the >>>>>> iris core on the SM8550 platform. The major difference is that glymur >>>>>> integrates two codec cores (vcodec0 and vcodec1), while SM8550 has only >>>>>> one. Add glymur specific platform data, reusing SM8550 definitions >>>>>> wherever applicable. >>>>> This leave me in confusion. Having two cores, each with its own set of >>>>> clocks and pm domains, I'd have expected that each core scales >>>>> independently. I.e. if the load is pushed to the core0, it requires >>>>> core0 clocks to go higher (while core1 clocks can stay at the low freq). >>>>> Or, at least, the clocks would be set to the frequency corresponding to >>>>> the max of the workloads (if for some reason the cores should stay in >>>>> sync). >>>>> >>>>> However, I don't see it in the code. All clocks and all power domains >>>>> seem do be scaled using the common workload. If my assumptions were not >>>>> correct, please explain it in the commit message. >>>> >>>> The OPP core logic sets the rpmhpd level and clock rate based on the OPP table >>>> defined in the DT node, where the clock frequency and power rail level are >>>> tightly coupled together. Since vcodec0 and vcodec1 share the same power rails, >>>> independently scaling one clock high while keeping the other low is not >>>> straightforward within this OPP framework. >>>> >>>> Do you have any suggestion on how best to handle per core independent clock >>>> scaling within these constraints? >>> >>> This would require more plumbing and driver changes, but: >>> >>> iris: video-codec@foo { >>> compatible = "qcom,glymur-iris", >>> clocks = ; >>> resets = ; >>> >>> /* or core@0 */ >>> codec@0 { >>> clocks, resets, power-domains; >>> operating-points-v2 = <&iris_opp_table> >>> }; >>> >>> /* or core@1 */ >>> codec@1 { >>> clocks, resets, power-domains; >>> operating-points-v2 = <&iris_opp_table> >>> }; >>> >>> iris_opp_table: opp-table { >>> compatible = "operating-points-v2" >>> }; >>> }; >>> >> >> clock source "video_cc_mvs0_clk_src" is common for both the cores. It would >> not matter if core0 is scaled for a specific workload and core1 is scaled >> for different (let say lower), as the common PLL would always generate the >> higher of them. >> >> Infact, going with the approach of exclusive scaling would be an issue here. >> The later core scaling command would bring down/up the corner for other >> core, and could lead to under/over-voting. > > Are the dividers between mvs0_clk_src and the branch clocks really R/O > in the hardware? Can they be scaled to account for the different > workloads? dividers div ratio is pre-fixed in nature, does not vary with workload. Again, you need to look at the source clock, rather than the ones at different core. Even if they are scaled differently, either in software or hardware (assume for now, hw does), the source would always pick the higher of the scaled frequency corner. > The commit message should capture the details of the > interaction between cores: > - Can either of them be turned off, while retaining the other one > running? > - Can either of them run at a different frequency than the other one? > - etc. Lets capture these details in the patch which enables the power sequence for the dual core. > >>>> >>>>>> Reviewed-by: Vikash Garodia >>>>>> Signed-off-by: Vishnu Reddy >>>>>> --- >>>>>> drivers/media/platform/qcom/iris/Makefile | 1 + >>>>>> .../platform/qcom/iris/iris_platform_common.h | 5 ++ >>>>>> .../media/platform/qcom/iris/iris_platform_gen2.c | 99 ++++++++++++++++++++++ >>>>>> .../platform/qcom/iris/iris_platform_glymur.c | 97 +++++++++++++++++++++ >>>>>> .../platform/qcom/iris/iris_platform_glymur.h | 17 ++++ >>>>>> drivers/media/platform/qcom/iris/iris_probe.c | 4 + >>>>>> 6 files changed, 223 insertions(+) >>>>>> >>> >> >