[PATCH 0/4] IPQ8074 pcie/wcss fixes

[PATCH 0/4] IPQ8074 pcie/wcss fixes

[Sricharan Ramabadhran]

These are required to have pcie/wcss working on IPQ8074 based
boards. Pcie was broken recently, first patch fixes that and
next 2 are for adding WCSS reset and 1 for adding reserved region
for NSS.

Will be following this up with few more dts updates and pcie
fixes.

Sricharan Ramabadhran (4):
  pcie: qcom: Fix the macro PARF_SLV_ADDR_SPACE_SIZE_2_3_3
  dt-bindings: clock: qcom: Add reset for WCSSAON
  clk: qcom: Add WCSSAON reset
  dts: Reserve memory region for NSS and TZ

 arch/arm64/boot/dts/qcom/ipq8074.dtsi        | 7 ++++++-
 drivers/clk/qcom/gcc-ipq8074.c               | 1 +
 drivers/pci/controller/dwc/pcie-qcom.c       | 2 +-
 include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 +
 4 files changed, 9 insertions(+), 2 deletions(-)

-- 
2.34.1

[PATCH 1/4] pcie: qcom: Fix the macro PARF_SLV_ADDR_SPACE_SIZE_2_3_3

[Sricharan Ramabadhran]

PARF_SLV_ADDR_SPACE_SIZE_2_3_3 macro used for IPQ8074
pcie slave addr size was initially set to 0x358, but
was wrongly changed to 0x168 as a part of
'PCI: qcom: Sort and group registers and bitfield definitions'
Fixing it back to right value here.

Without this pcie bring up on IPQ8074 is broken now.

Fixes: 769e49d87b15 ("PCI: qcom: Sort and group registers and bitfield definitions")
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 4ab30892f6ef..59823beed13f 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -43,7 +43,7 @@
 #define PARF_PHY_REFCLK				0x4c
 #define PARF_CONFIG_BITS			0x50
 #define PARF_DBI_BASE_ADDR			0x168
-#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x16c /* Register offset specific to IP ver 2.3.3 */
+#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x358 /* Register offset specific to IP ver 2.3.3 */
 #define PARF_MHI_CLOCK_RESET_CTRL		0x174
 #define PARF_AXI_MSTR_WR_ADDR_HALT		0x178
 #define PARF_AXI_MSTR_WR_ADDR_HALT_V2		0x1a8
-- 
2.34.1

Re: [PATCH 1/4] pcie: qcom: Fix the macro PARF_SLV_ADDR_SPACE_SIZE_2_3_3

[Konrad Dybcio]

On 23.06.2023 11:44, Sricharan Ramabadhran wrote:
> PARF_SLV_ADDR_SPACE_SIZE_2_3_3 macro used for IPQ8074
> pcie slave addr size was initially set to 0x358, but
> was wrongly changed to 0x168 as a part of
> 'PCI: qcom: Sort and group registers and bitfield definitions'
Surely not, this commit only moved the definition containing 0x358 up.

Konrad
> Fixing it back to right value here.
> 
> Without this pcie bring up on IPQ8074 is broken now.
> 
> Fixes: 769e49d87b15 ("PCI: qcom: Sort and group registers and bitfield definitions")
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> ---
>  drivers/pci/controller/dwc/pcie-qcom.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 4ab30892f6ef..59823beed13f 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -43,7 +43,7 @@
>  #define PARF_PHY_REFCLK				0x4c
>  #define PARF_CONFIG_BITS			0x50
>  #define PARF_DBI_BASE_ADDR			0x168
> -#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x16c /* Register offset specific to IP ver 2.3.3 */
> +#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x358 /* Register offset specific to IP ver 2.3.3 */
>  #define PARF_MHI_CLOCK_RESET_CTRL		0x174
>  #define PARF_AXI_MSTR_WR_ADDR_HALT		0x178
>  #define PARF_AXI_MSTR_WR_ADDR_HALT_V2		0x1a8

Re: [PATCH 1/4] pcie: qcom: Fix the macro PARF_SLV_ADDR_SPACE_SIZE_2_3_3

[Sricharan Ramabadhran]

On 6/23/2023 3:52 PM, Konrad Dybcio wrote:
> On 23.06.2023 11:44, Sricharan Ramabadhran wrote:
>> PARF_SLV_ADDR_SPACE_SIZE_2_3_3 macro used for IPQ8074
>> pcie slave addr size was initially set to 0x358, but
>> was wrongly changed to 0x168 as a part of
>> 'PCI: qcom: Sort and group registers and bitfield definitions'
> Surely not, this commit only moved the definition containing 0x358 up.
> 

   Oops, infact it was the one just below, this one which changed it.

    "PCI: qcom: Remove PCIE20_ prefix from register definitions"

  Will fix this in V2.

Regards,
  Sricharan

> Konrad
>> Fixing it back to right value here.
>>
>> Without this pcie bring up on IPQ8074 is broken now.
>>
>> Fixes: 769e49d87b15 ("PCI: qcom: Sort and group registers and bitfield definitions")
>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>> ---
>>   drivers/pci/controller/dwc/pcie-qcom.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
>> index 4ab30892f6ef..59823beed13f 100644
>> --- a/drivers/pci/controller/dwc/pcie-qcom.c
>> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
>> @@ -43,7 +43,7 @@
>>   #define PARF_PHY_REFCLK				0x4c
>>   #define PARF_CONFIG_BITS			0x50
>>   #define PARF_DBI_BASE_ADDR			0x168
>> -#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x16c /* Register offset specific to IP ver 2.3.3 */
>> +#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x358 /* Register offset specific to IP ver 2.3.3 */
>>   #define PARF_MHI_CLOCK_RESET_CTRL		0x174
>>   #define PARF_AXI_MSTR_WR_ADDR_HALT		0x178
>>   #define PARF_AXI_MSTR_WR_ADDR_HALT_V2		0x1a8

[PATCH 2/4] dt-bindings: clock: qcom: Add reset for WCSSAON

[Sricharan Ramabadhran]

Add binding for WCSSAON reset required for Q6v5 reset on IPQ8074 SoC.

Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
---
 Previous post was here
	https://lore.kernel.org/linux-arm-msm/20190724203737.GA27783@bogus/

 include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
index f9ea55811104..e47cbf7394aa 100644
--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
@@ -381,6 +381,7 @@
 #define GCC_NSSPORT4_RESET			143
 #define GCC_NSSPORT5_RESET			144
 #define GCC_NSSPORT6_RESET			145
+#define GCC_WCSSAON_RESET			146
 
 #define USB0_GDSC				0
 #define USB1_GDSC				1
-- 
2.34.1

[PATCH 3/4] clk: qcom: Add WCSSAON reset

[Sricharan Ramabadhran]

Add WCSSAON reset required for Q6v5 on IPQ8074 SoC.

Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
---
 Previous post was here
	https://lore.kernel.org/linux-arm-msm/20190717200910.1E93C20880@mail.kernel.org/

 drivers/clk/qcom/gcc-ipq8074.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
index 6541d98c0348..910aec33a871 100644
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -4685,6 +4685,7 @@ static const struct qcom_reset_map gcc_ipq8074_resets[] = {
 	[GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = BIT(27) | GENMASK(9, 8) },
 	[GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = BIT(28) | GENMASK(11, 10) },
 	[GCC_NSSPORT6_RESET] = { .reg = 0x68014, .bitmask = BIT(29) | GENMASK(13, 12) },
+	[GCC_WCSSAON_RESET]  = { 0x59010, 0 },
 };
 
 static struct gdsc *gcc_ipq8074_gdscs[] = {
-- 
2.34.1

[PATCH 4/4] dts: Reserve memory region for NSS and TZ

[Sricharan Ramabadhran]

Add reserved memory region for NSS and fix the name
for tz region explicitly.

Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 791af73334cb..d51ff9b4f5c1 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -86,6 +86,11 @@ reserved-memory {
 		#size-cells = <2>;
 		ranges;
 
+		nss@40000000 {
+			reg = <0x0 0x40000000 0x0 0x01000000>;
+			no-map;
+		};
+
 		bootloader@4a600000 {
 			reg = <0x0 0x4a600000 0x0 0x400000>;
 			no-map;
@@ -104,7 +109,7 @@ smem@4ab00000 {
 			hwlocks = <&tcsr_mutex 0>;
 		};
 
-		memory@4ac00000 {
+		tz@4ac00000 {
 			reg = <0x0 0x4ac00000 0x0 0x400000>;
 			no-map;
 		};
-- 
2.34.1

Re: [PATCH 4/4] dts: Reserve memory region for NSS and TZ

[Krzysztof Kozlowski]

On 23/06/2023 11:44, Sricharan Ramabadhran wrote:
> Add reserved memory region for NSS and fix the name
> for tz region explicitly.
> 
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>

Please use subject prefixes matching the subsystem. You can get them for
example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
your patch is touching.

Best regards,
Krzysztof

Re: [PATCH 4/4] dts: Reserve memory region for NSS and TZ

[Sricharan Ramabadhran]

On 6/23/2023 3:50 PM, Krzysztof Kozlowski wrote:
> On 23/06/2023 11:44, Sricharan Ramabadhran wrote:
>> Add reserved memory region for NSS and fix the name
>> for tz region explicitly.
>>
>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> 
> Please use subject prefixes matching the subsystem. You can get them for
> example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
> your patch is touching.
> 

  Sure, will fix in V2

Regards,
  Sricharan

Re: [PATCH 4/4] dts: Reserve memory region for NSS and TZ

[Konrad Dybcio]

On 23.06.2023 11:44, Sricharan Ramabadhran wrote:
> Add reserved memory region for NSS and fix the name
> for tz region explicitly.
> 
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> ---
The commit title is divergent from what's in the commit message and
the patch body. Please separate these two changes.

>  arch/arm64/boot/dts/qcom/ipq8074.dtsi | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> index 791af73334cb..d51ff9b4f5c1 100644
> --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> @@ -86,6 +86,11 @@ reserved-memory {
>  		#size-cells = <2>;
>  		ranges;
>  
> +		nss@40000000 {
> +			reg = <0x0 0x40000000 0x0 0x01000000>;
Drop the leading zeroes from the size part.

Konrad
> +			no-map;
> +		};
> +
>  		bootloader@4a600000 {
>  			reg = <0x0 0x4a600000 0x0 0x400000>;
>  			no-map;
> @@ -104,7 +109,7 @@ smem@4ab00000 {
>  			hwlocks = <&tcsr_mutex 0>;
>  		};
>  
> -		memory@4ac00000 {
> +		tz@4ac00000 {
>  			reg = <0x0 0x4ac00000 0x0 0x400000>;
>  			no-map;
>  		};

Re: [PATCH 4/4] dts: Reserve memory region for NSS and TZ

[Sricharan Ramabadhran]

On 6/23/2023 3:53 PM, Konrad Dybcio wrote:
> On 23.06.2023 11:44, Sricharan Ramabadhran wrote:
>> Add reserved memory region for NSS and fix the name
>> for tz region explicitly.
>>
>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>> ---
> The commit title is divergent from what's in the commit message and
> the patch body. Please separate these two changes.
> 
  ok, will split.

>>   arch/arm64/boot/dts/qcom/ipq8074.dtsi | 7 ++++++-
>>   1 file changed, 6 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> index 791af73334cb..d51ff9b4f5c1 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> @@ -86,6 +86,11 @@ reserved-memory {
>>   		#size-cells = <2>;
>>   		ranges;
>>   
>> +		nss@40000000 {
>> +			reg = <0x0 0x40000000 0x0 0x01000000>;
> Drop the leading zeroes from the size part.

  ok.

Regards,
  Sricharan

Re: [PATCH 0/4] IPQ8074 pcie/wcss fixes

[Konrad Dybcio]

On 23.06.2023 11:43, Sricharan Ramabadhran wrote:
> These are required to have pcie/wcss working on IPQ8074 based
> boards. Pcie was broken recently, first patch fixes that and
> next 2 are for adding WCSS reset and 1 for adding reserved region
> for NSS.
> 
> Will be following this up with few more dts updates and pcie
> fixes.
I got this patch series twice, once without patch 4. This one should
have contained the word RESEND after PATCH and the reasoning for resending
should have been put into the cover letter.

Konrad
> 
> Sricharan Ramabadhran (4):
>   pcie: qcom: Fix the macro PARF_SLV_ADDR_SPACE_SIZE_2_3_3
>   dt-bindings: clock: qcom: Add reset for WCSSAON
>   clk: qcom: Add WCSSAON reset
>   dts: Reserve memory region for NSS and TZ
> 
>  arch/arm64/boot/dts/qcom/ipq8074.dtsi        | 7 ++++++-
>  drivers/clk/qcom/gcc-ipq8074.c               | 1 +
>  drivers/pci/controller/dwc/pcie-qcom.c       | 2 +-
>  include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 +
>  4 files changed, 9 insertions(+), 2 deletions(-)
> 

[PATCH 0/4] IPQ8074 pcie/wcss fixes

[Sricharan Ramabadhran]

These are required to have pcie/wcss working on IPQ8074 based
boards. Pcie was broken recently, first patch fixes that and
next 2 are for adding WCSS reset and 1 for adding reserved region
for NSS.

Will be following this up with few more dts updates and pcie
fixes.

Sricharan Ramabadhran (4):
  pcie: qcom: Fix the macro PARF_SLV_ADDR_SPACE_SIZE_2_3_3
  dt-bindings: clock: qcom: Add reset for WCSSAON
  clk: qcom: Add WCSSAON reset
  dts: Reserve memory region for NSS and TZ

 arch/arm64/boot/dts/qcom/ipq8074.dtsi        | 7 ++++++-
 drivers/clk/qcom/gcc-ipq8074.c               | 1 +
 drivers/pci/controller/dwc/pcie-qcom.c       | 2 +-
 include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 +
 4 files changed, 9 insertions(+), 2 deletions(-)

-- 
2.34.1

[PATCH 1/4] pcie: qcom: Fix the macro PARF_SLV_ADDR_SPACE_SIZE_2_3_3

[Sricharan Ramabadhran]

PARF_SLV_ADDR_SPACE_SIZE_2_3_3 macro used for IPQ8074
pcie slave addr size was initially set to 0x358, but
was wrongly changed to 0x168 as a part of
'PCI: qcom: Sort and group registers and bitfield definitions'
Fixing it back to right value here.

Without this pcie bring up on IPQ8074 is broken now.

Fixes: 769e49d87b15 ("PCI: qcom: Sort and group registers and bitfield definitions")
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 4ab30892f6ef..59823beed13f 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -43,7 +43,7 @@
 #define PARF_PHY_REFCLK				0x4c
 #define PARF_CONFIG_BITS			0x50
 #define PARF_DBI_BASE_ADDR			0x168
-#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x16c /* Register offset specific to IP ver 2.3.3 */
+#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x358 /* Register offset specific to IP ver 2.3.3 */
 #define PARF_MHI_CLOCK_RESET_CTRL		0x174
 #define PARF_AXI_MSTR_WR_ADDR_HALT		0x178
 #define PARF_AXI_MSTR_WR_ADDR_HALT_V2		0x1a8
-- 
2.34.1

Re: [PATCH 1/4] pcie: qcom: Fix the macro PARF_SLV_ADDR_SPACE_SIZE_2_3_3

[Bjorn Helgaas]

On Fri, Jun 23, 2023 at 03:04:42PM +0530, Sricharan Ramabadhran wrote:
> PARF_SLV_ADDR_SPACE_SIZE_2_3_3 macro used for IPQ8074
> pcie slave addr size was initially set to 0x358, but
> was wrongly changed to 0x168 as a part of
> 'PCI: qcom: Sort and group registers and bitfield definitions'
> Fixing it back to right value here.
> 
> Without this pcie bring up on IPQ8074 is broken now.
> 
> Fixes: 769e49d87b15 ("PCI: qcom: Sort and group registers and bitfield definitions")

769e49d87b15 appeared in v6.4-rc1, so ideally this would get merged
before v6.4 releases on Monday.  I can try to do that, given an ack
from Manivannan.

> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> ---
>  drivers/pci/controller/dwc/pcie-qcom.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 4ab30892f6ef..59823beed13f 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -43,7 +43,7 @@
>  #define PARF_PHY_REFCLK				0x4c
>  #define PARF_CONFIG_BITS			0x50
>  #define PARF_DBI_BASE_ADDR			0x168
> -#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x16c /* Register offset specific to IP ver 2.3.3 */
> +#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x358 /* Register offset specific to IP ver 2.3.3 */
>  #define PARF_MHI_CLOCK_RESET_CTRL		0x174
>  #define PARF_AXI_MSTR_WR_ADDR_HALT		0x178
>  #define PARF_AXI_MSTR_WR_ADDR_HALT_V2		0x1a8
> -- 
> 2.34.1
> 

Re: [PATCH 1/4] pcie: qcom: Fix the macro PARF_SLV_ADDR_SPACE_SIZE_2_3_3

[Bjorn Helgaas]

On Fri, Jun 23, 2023 at 03:04:42PM +0530, Sricharan Ramabadhran wrote:
> PARF_SLV_ADDR_SPACE_SIZE_2_3_3 macro used for IPQ8074
> pcie slave addr size was initially set to 0x358, but
> was wrongly changed to 0x168 as a part of
> 'PCI: qcom: Sort and group registers and bitfield definitions'
> Fixing it back to right value here.

1) Make your subject line match the history.  For example, you're
fixing 769e49d87b15 ("PCI: qcom: Sort and group registers ..."), so
your subject line should start with "PCI: qcom: ...".

2) It doesn't look like 769e49d87b15 changed
PARF_SLV_ADDR_SPACE_SIZE_2_3_3:

  $ git show 769e49d87b15 | grep PARF_SLV_ADDR_SPACE_SIZE_2_3_3
  +#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x16C /* Register offset specific to IP ver 2.3.3 */
  -#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x16C /* Register offset specific to IP rev 2.3.3 */

What am I missing here?  Do you have another out-of-tree patch that
broke this?

Bjorn

> Without this pcie bring up on IPQ8074 is broken now.
> 
> Fixes: 769e49d87b15 ("PCI: qcom: Sort and group registers and bitfield definitions")
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> ---
>  drivers/pci/controller/dwc/pcie-qcom.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 4ab30892f6ef..59823beed13f 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -43,7 +43,7 @@
>  #define PARF_PHY_REFCLK				0x4c
>  #define PARF_CONFIG_BITS			0x50
>  #define PARF_DBI_BASE_ADDR			0x168
> -#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x16c /* Register offset specific to IP ver 2.3.3 */
> +#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x358 /* Register offset specific to IP ver 2.3.3 */
>  #define PARF_MHI_CLOCK_RESET_CTRL		0x174
>  #define PARF_AXI_MSTR_WR_ADDR_HALT		0x178
>  #define PARF_AXI_MSTR_WR_ADDR_HALT_V2		0x1a8
> -- 
> 2.34.1
> 

Re: [PATCH 1/4] pcie: qcom: Fix the macro PARF_SLV_ADDR_SPACE_SIZE_2_3_3

[Sricharan Ramabadhran]

Hi Bjorn,

On 6/23/2023 11:30 PM, Bjorn Helgaas wrote:
> On Fri, Jun 23, 2023 at 03:04:42PM +0530, Sricharan Ramabadhran wrote:
>> PARF_SLV_ADDR_SPACE_SIZE_2_3_3 macro used for IPQ8074
>> pcie slave addr size was initially set to 0x358, but
>> was wrongly changed to 0x168 as a part of
>> 'PCI: qcom: Sort and group registers and bitfield definitions'
>> Fixing it back to right value here.
> 
> 1) Make your subject line match the history.  For example, you're
> fixing 769e49d87b15 ("PCI: qcom: Sort and group registers ..."), so
> your subject line should start with "PCI: qcom: ...".
> 

  ok, will fix.

> 2) It doesn't look like 769e49d87b15 changed
> PARF_SLV_ADDR_SPACE_SIZE_2_3_3:
> 
>    $ git show 769e49d87b15 | grep PARF_SLV_ADDR_SPACE_SIZE_2_3_3
>    +#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x16C /* Register offset specific to IP ver 2.3.3 */
>    -#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x16C /* Register offset specific to IP rev 2.3.3 */
> 
> What am I missing here?  Do you have another out-of-tree patch that
> broke this?

  39171b33f652 ("PCI: qcom: Remove PCIE20_ prefix from
                register definitions") broke it. Will change and post .

Regards,
  Sricharan

Re: [PATCH 1/4] pcie: qcom: Fix the macro PARF_SLV_ADDR_SPACE_SIZE_2_3_3

[Manivannan Sadhasivam]

On Fri, Jun 23, 2023 at 03:04:42PM +0530, Sricharan Ramabadhran wrote:
> PARF_SLV_ADDR_SPACE_SIZE_2_3_3 macro used for IPQ8074
> pcie slave addr size was initially set to 0x358, but
> was wrongly changed to 0x168 as a part of
> 'PCI: qcom: Sort and group registers and bitfield definitions'
> Fixing it back to right value here.
> 
> Without this pcie bring up on IPQ8074 is broken now.
> 

Subject prefix should be: "PCI: qcom: "

> Fixes: 769e49d87b15 ("PCI: qcom: Sort and group registers and bitfield definitions")

Fixes tag is referring to a wrong commit. Correct one is:
39171b33f652 ("PCI: qcom: Remove PCIE20_ prefix from register definitions")

> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> ---
>  drivers/pci/controller/dwc/pcie-qcom.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 4ab30892f6ef..59823beed13f 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -43,7 +43,7 @@
>  #define PARF_PHY_REFCLK				0x4c
>  #define PARF_CONFIG_BITS			0x50
>  #define PARF_DBI_BASE_ADDR			0x168
> -#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x16c /* Register offset specific to IP ver 2.3.3 */
> +#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x358 /* Register offset specific to IP ver 2.3.3 */

You should just remove PARF_SLV_ADDR_SPACE_SIZE_2_3_3 and use
PARF_SLV_ADDR_SPACE_SIZE which already has the value of 0x358.

- Mani

>  #define PARF_MHI_CLOCK_RESET_CTRL		0x174
>  #define PARF_AXI_MSTR_WR_ADDR_HALT		0x178
>  #define PARF_AXI_MSTR_WR_ADDR_HALT_V2		0x1a8
> -- 
> 2.34.1
> 

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH 1/4] pcie: qcom: Fix the macro PARF_SLV_ADDR_SPACE_SIZE_2_3_3

[Sricharan Ramabadhran]

On 6/24/2023 12:02 PM, Manivannan Sadhasivam wrote:
> On Fri, Jun 23, 2023 at 03:04:42PM +0530, Sricharan Ramabadhran wrote:
>> PARF_SLV_ADDR_SPACE_SIZE_2_3_3 macro used for IPQ8074
>> pcie slave addr size was initially set to 0x358, but
>> was wrongly changed to 0x168 as a part of
>> 'PCI: qcom: Sort and group registers and bitfield definitions'
>> Fixing it back to right value here.
>>
>> Without this pcie bring up on IPQ8074 is broken now.
>>
> 
> Subject prefix should be: "PCI: qcom: "
> 
>> Fixes: 769e49d87b15 ("PCI: qcom: Sort and group registers and bitfield definitions")
> 
> Fixes tag is referring to a wrong commit. Correct one is:
> 39171b33f652 ("PCI: qcom: Remove PCIE20_ prefix from register definitions")
> 

  ok.

>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>> ---
>>   drivers/pci/controller/dwc/pcie-qcom.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
>> index 4ab30892f6ef..59823beed13f 100644
>> --- a/drivers/pci/controller/dwc/pcie-qcom.c
>> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
>> @@ -43,7 +43,7 @@
>>   #define PARF_PHY_REFCLK				0x4c
>>   #define PARF_CONFIG_BITS			0x50
>>   #define PARF_DBI_BASE_ADDR			0x168
>> -#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x16c /* Register offset specific to IP ver 2.3.3 */
>> +#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x358 /* Register offset specific to IP ver 2.3.3 */
> 
> You should just remove PARF_SLV_ADDR_SPACE_SIZE_2_3_3 and use
> PARF_SLV_ADDR_SPACE_SIZE which already has the value of 0x358.
> 

  ok

Regards,
  Sricharan