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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id 11-20020a056000156b00b002040674fd13sm20116879wrz.38.2022.04.07.01.30.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 07 Apr 2022 01:30:57 -0700 (PDT) Message-ID: Date: Thu, 7 Apr 2022 10:30:56 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v0 01/10] drm/bridge: dw-hdmi: add low-active PHY reset Content-Language: en-US To: Lucas Stach , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Shawn Guo , NXP Linux Team Cc: Fabio Estevam , Pengutronix Kernel Team , Robert Foss , Andrzej Hajda , Vinod Koul , Kishon Vijay Abraham I , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, patchwork-lst@pengutronix.de References: <20220406160123.1272911-1-l.stach@pengutronix.de> <20220406160123.1272911-2-l.stach@pengutronix.de> From: Neil Armstrong Organization: Baylibre In-Reply-To: <20220406160123.1272911-2-l.stach@pengutronix.de> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Lucas, On 06/04/2022 18:01, Lucas Stach wrote: > Allow vendor PHY implementations to reset PHYs with different polarity > than the current Gen2 reset. > > Signed-off-by: Lucas Stach > --- > drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 7 +++++++ > include/drm/bridge/dw_hdmi.h | 1 + > 2 files changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c > index 4befc104d220..7600f26aab27 100644 > --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c > +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c > @@ -1365,6 +1365,13 @@ void dw_hdmi_phy_reset(struct dw_hdmi *hdmi) > } > EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset); > > +void dw_hdmi_phy_reset_active_low(struct dw_hdmi *hdmi) > +{ > + hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); > + hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); > +} > +EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset_active_low); > + > void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address) > { > hdmi_phy_test_clear(hdmi, 1); > diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h > index 2a1f85f9a8a3..9b3d52a1e62a 100644 > --- a/include/drm/bridge/dw_hdmi.h > +++ b/include/drm/bridge/dw_hdmi.h > @@ -190,6 +190,7 @@ void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, > void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable); > void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable); > void dw_hdmi_phy_reset(struct dw_hdmi *hdmi); > +void dw_hdmi_phy_reset_active_low(struct dw_hdmi *hdmi); > > enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, > void *data); This has already been submitted at https://lore.kernel.org/r/800262112191a720639ba321be18f0926d4e1d2a.1649230434.git.Sandor.yu@nxp.com