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Wed, 27 Nov 2024 09:56:58 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AR9uw5D001804 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 27 Nov 2024 09:56:58 GMT Received: from [10.64.68.102] (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 27 Nov 2024 01:56:48 -0800 Message-ID: Date: Wed, 27 Nov 2024 17:56:45 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/5] arm64: dts: qcom: qcs8300: enable pcie0 for QCS8300 To: Konrad Dybcio , , , , , , , , , , , , CC: , , , , , , , , , References: <20241114095409.2682558-1-quic_ziyuzhan@quicinc.com> <20241114095409.2682558-5-quic_ziyuzhan@quicinc.com> Content-Language: en-US From: Ziyue Zhang In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: tTg52swv73q9BIT9C6iEByOmYqdiO0Sv X-Proofpoint-ORIG-GUID: tTg52swv73q9BIT9C6iEByOmYqdiO0Sv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 mlxlogscore=999 spamscore=0 adultscore=0 malwarescore=0 impostorscore=0 phishscore=0 priorityscore=1501 mlxscore=0 suspectscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411270082 On 11/14/2024 9:02 PM, Konrad Dybcio wrote: > On 14.11.2024 10:54 AM, Ziyue Zhang wrote: >> Add configurations in devicetree for PCIe0, including registers, clocks, >> interrupts and phy setting sequence. >> >> Signed-off-by: Ziyue Zhang >> --- >> arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 44 +++++- >> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 176 ++++++++++++++++++++++ > This implies this patch should be two separate ones > > > [...] > > >> +&tlmm { >> + pcie0_default_state: pcie0-default-state { >> + perst-pins { >> + pins = "gpio2"; >> + function = "gpio"; >> + drive-strength = <2>; >> + bias-pull-down; >> + }; >> + >> + clkreq-pins { >> + pins = "gpio1"; >> + function = "pcie0_clkreq"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + wake-pins { >> + pins = "gpio0"; > Sorting these in an increasing order would be welcome > > >> >> + pcie0: pci@1c00000 { >> + compatible = "qcom,pcie-qcs8300","qcom,pcie-sa8775p"; > Missing ' ' after ',' > >> + reg = <0x0 0x01c00000 0x0 0x3000>, >> + <0x0 0x40000000 0x0 0xf20>, >> + <0x0 0x40000f20 0x0 0xa8>, >> + <0x0 0x40001000 0x0 0x4000>, >> + <0x0 0x40100000 0x0 0x100000>, >> + <0x0 0x01c03000 0x0 0x1000>; >> + >> + reg-names = "parf", >> + "dbi", >> + "elbi", >> + "atu", >> + "config", >> + "mhi"; >> + >> + device_type = "pci"; > Please try to match the style in x1e80100, it's mostly coherent but > things like newlines differ, which is tiny but mildly annoying > >> + >> + #address-cells = <3>; >> + #size-cells = <2>; >> + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, >> + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; > Looks like there's a bit more space in there >> + bus-range = <0x00 0xff>; >> + >> + dma-coherent; >> + >> + linux,pci-domain = <0>; >> + num-lanes = <2>; >> + >> + interrupts = , >> + , >> + , >> + , >> + , >> + , >> + , >> + ; >> + >> + interrupt-names = "msi0", >> + "msi1", >> + "msi2", >> + "msi3", >> + "msi4", >> + "msi5", >> + "msi6", >> + "msi7"; > Please also add a "global" interrupt.. looks like it's GIC_SPI 166, but > please confirm > okay >> + >> + #interrupt-cells = <1>; >> + interrupt-map-mask = <0 0 0 0x7>; >> + interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, >> + <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, >> + <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, >> + <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, >> + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, >> + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, >> + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, >> + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; >> + >> + clock-names = "aux", >> + "cfg", >> + "bus_master", >> + "bus_slave", >> + "slave_q2a"; >> + >> + assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; >> + assigned-clock-rates = <19200000>; >> + >> + interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, > QCOM_ICC_TAG_ALWAYS > okay >> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; > QCOM_ICC_TAG_ACTIVE_ONLY > > [...] > okay >> + >> + pcieport0: pcie@0 { >> + device_type = "pci"; >> + reg = <0x0 0x0 0x0 0x0 0x0>; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + ranges; >> + bus-range = <0x01 0xff>; >> + }; > Are you going to use this? If not, please drop its required by wlan driver we need it BRs Ziyue > >> + }; >> + >> + pcie0_phy: phy@1c04000 { >> + compatible = "qcom,qcs8300-qmp-gen4x2-pcie-phy"; >> + reg = <0x0 0x1c04000 0x0 0x2000>; >> + >> + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, > This clock goes to the RC, it should be _PHY_AUX (which you put below > as phy_aux), please replace it. > will do it >> + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, >> + <&gcc GCC_PCIE_CLKREF_EN>, >> + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, >> + <&gcc GCC_PCIE_0_PIPE_CLK>, >> + <&gcc GCC_PCIE_0_PIPEDIV2_CLK>, >> + <&gcc GCC_PCIE_0_PHY_AUX_CLK>; >> + >> + clock-names = "aux", >> + "cfg_ahb", >> + "ref", >> + "rchng", >> + "pipe", >> + "pipediv2", >> + "phy_aux"; > Konrad