From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D485EC18E5A for ; Tue, 10 Mar 2020 16:16:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B082321D56 for ; Tue, 10 Mar 2020 16:16:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727018AbgCJQQT (ORCPT ); Tue, 10 Mar 2020 12:16:19 -0400 Received: from foss.arm.com ([217.140.110.172]:39112 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726395AbgCJQQS (ORCPT ); Tue, 10 Mar 2020 12:16:18 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5FF9F1FB; Tue, 10 Mar 2020 09:16:18 -0700 (PDT) Received: from [10.1.196.37] (e121345-lin.cambridge.arm.com [10.1.196.37]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C81913F67D; Tue, 10 Mar 2020 09:16:16 -0700 (PDT) Subject: Re: [PATCH] ARM: dts: dra7: Add bus_dma_limit for L3 bus To: Tony Lindgren , Tero Kristo Cc: Roger Quadros , hch@lst.de, robh+dt@kernel.org, nm@ti.com, nsekhar@ti.com, linux-omap@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20200310115309.31354-1-rogerq@ti.com> <20200310154829.GS37466@atomide.com> From: Robin Murphy Message-ID: Date: Tue, 10 Mar 2020 16:16:14 +0000 User-Agent: Mozilla/5.0 (X11; Linux aarch64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <20200310154829.GS37466@atomide.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 10/03/2020 3:48 pm, Tony Lindgren wrote: > * Tero Kristo [200310 14:46]: >> On 10/03/2020 13:53, Roger Quadros wrote: >>> The L3 interconnect can access only 32-bits of address. >>> Add the dma-ranges property to reflect this limit. >>> >>> This will ensure that no device under L3 is >>> given > 32-bit address for DMA. >>> >>> Issue was observed only with SATA on DRA7-EVM with 4GB RAM >>> and CONFIG_ARM_LPAE enabled. This is because the controller >>> can perform 64-bit DMA and was setting the dma_mask to 64-bit. >>> >>> Setting the correct bus_dma_limit fixes the issue. >> >> This seems kind of messy to modify almost every DT node because of this.... >> Are you sure this is the only way to get it done? No way to modify the sata >> node only which is impacted somehow? >> >> Also, what if you just pass 0xffffffff to the dma-ranges property? That >> would avoid modifying every node I guess. > > Also, I think these interconnects are not limited to 32-bit access. > So yeah I too would prefer a top level dma-ranges property assuming > that works. > > I guess there dma-ranges should not be 0xffffffff though if > limited to 2GB :) It should work fine to just describe the Q3 and Q4 DDR regions as the DMA range, i.e.: ocp { ... dma-ranges = <0x80000000 0 0x80000000 0x80000000>; ... }; That would certainly be far less invasive :) Robin.