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Tue, 30 Sep 2025 05:36:18 -0700 (PDT) Message-ID: Subject: Re: [PATCH v2 2/6] iio: adc: ad4080: prepare driver for multi-part support From: Nuno =?ISO-8859-1?Q?S=E1?= To: Antoniu Miclaus , jic23@kernel.org, robh@kernel.org, conor+dt@kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Date: Tue, 30 Sep 2025 13:36:46 +0100 In-Reply-To: <20250930103229.28696-2-antoniu.miclaus@analog.com> References: <20250930103229.28696-1-antoniu.miclaus@analog.com> <20250930103229.28696-2-antoniu.miclaus@analog.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.58.0 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Tue, 2025-09-30 at 10:32 +0000, Antoniu Miclaus wrote: > Refactor the ad4080 driver to support multiple ADC variants with > different resolution bits and LVDS CNV clock count maximums. >=20 > Changes: > - Add lvds_cnv_clk_cnt_max field to chip_info structure > - Create AD4080_CHANNEL_DEFINE macro for variable resolution/storage bits > - Make LVDS CNV clock count configurable per chip variant > - Use chip_info->product_id for chip identification comparison >=20 > This prepares the infrastructure for adding support for additional > ADC parts with different specifications while maintaining backward > compatibility with existing AD4080 functionality. >=20 > Signed-off-by: Antoniu Miclaus > --- Reviewed-by: Nuno S=C3=A1 > changes in v2: > =C2=A0- allign all the \ to the left in the channel definition. > =C2=A0drivers/iio/adc/ad4080.c | 42 ++++++++++++++++++++++---------------= --- > =C2=A01 file changed, 23 insertions(+), 19 deletions(-) >=20 > diff --git a/drivers/iio/adc/ad4080.c b/drivers/iio/adc/ad4080.c > index b80560aebe2d..fa15b8f63b8a 100644 > --- a/drivers/iio/adc/ad4080.c > +++ b/drivers/iio/adc/ad4080.c > @@ -167,6 +167,7 @@ struct ad4080_chip_info { > =C2=A0 const unsigned int (*scale_table)[2]; > =C2=A0 const struct iio_chan_spec *channels; > =C2=A0 unsigned int num_channels; > + unsigned int lvds_cnv_clk_cnt_max; > =C2=A0}; > =C2=A0 > =C2=A0struct ad4080_state { > @@ -414,23 +415,25 @@ static struct iio_chan_spec_ext_info ad4080_ext_inf= o[] =3D > { > =C2=A0 { } > =C2=A0}; > =C2=A0 > -static const struct iio_chan_spec ad4080_channel =3D { > - .type =3D IIO_VOLTAGE, > - .indexed =3D 1, > - .channel =3D 0, > - .info_mask_separate =3D BIT(IIO_CHAN_INFO_SCALE), > - .info_mask_shared_by_all =3D BIT(IIO_CHAN_INFO_SAMP_FREQ) | > - BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), > - .info_mask_shared_by_all_available =3D > - BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), > - .ext_info =3D ad4080_ext_info, > - .scan_index =3D 0, > - .scan_type =3D { > - .sign =3D 's', > - .realbits =3D 20, > - .storagebits =3D 32, > - }, > -}; > +#define AD4080_CHANNEL_DEFINE(bits, storage) { \ > + .type =3D IIO_VOLTAGE, \ > + .indexed =3D 1, \ > + .channel =3D 0, \ > + .info_mask_separate =3D > BIT(IIO_CHAN_INFO_SCALE), \ > + .info_mask_shared_by_all =3D BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ > + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ > + .info_mask_shared_by_all_available =3D \ > + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ > + .ext_info =3D ad4080_ext_info, \ > + .scan_index =3D 0, \ > + .scan_type =3D { \ > + .sign =3D 's', \ > + .realbits =3D (bits), \ > + .storagebits =3D (storage), \ > + }, \ > +} > + > +static const struct iio_chan_spec ad4080_channel =3D AD4080_CHANNEL_DEFI= NE(20, > 32); > =C2=A0 > =C2=A0static const struct ad4080_chip_info ad4080_chip_info =3D { > =C2=A0 .name =3D "ad4080", > @@ -439,6 +442,7 @@ static const struct ad4080_chip_info ad4080_chip_info= =3D { > =C2=A0 .num_scales =3D ARRAY_SIZE(ad4080_scale_table), > =C2=A0 .num_channels =3D 1, > =C2=A0 .channels =3D &ad4080_channel, > + .lvds_cnv_clk_cnt_max =3D AD4080_LVDS_CNV_CLK_CNT_MAX, > =C2=A0}; > =C2=A0 > =C2=A0static int ad4080_setup(struct iio_dev *indio_dev) > @@ -463,7 +467,7 @@ static int ad4080_setup(struct iio_dev *indio_dev) > =C2=A0 return ret; > =C2=A0 > =C2=A0 id =3D get_unaligned_le16(&id); > - if (id !=3D AD4080_CHIP_ID) > + if (id !=3D st->info->product_id) > =C2=A0 dev_info(dev, "Unrecognized CHIP_ID 0x%X\n", id); > =C2=A0 > =C2=A0 ret =3D regmap_set_bits(st->regmap, AD4080_REG_GPIO_CONFIG_A, > @@ -489,7 +493,7 @@ static int ad4080_setup(struct iio_dev *indio_dev) > =C2=A0 AD4080_REG_ADC_DATA_INTF_CONFIG_B, > =C2=A0 =09 > AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK, > =C2=A0 =09 > FIELD_PREP(AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK, > - =C2=A0=C2=A0=C2=A0 AD4080_LVDS_CNV_CLK_CNT_MAX)); > + =C2=A0=C2=A0=C2=A0 st->info->lvds_cnv_clk_cnt_max)); > =C2=A0 if (ret) > =C2=A0 return ret; > =C2=A0