From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Bartosz Golaszewski <brgl@bgdev.pl>,
Andy Gross <agross@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev,
Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Subject: Re: [PATCH 5/7] arm64: dts: qcom: sa8775p: add the pcie smmu node
Date: Wed, 29 Mar 2023 13:33:09 +0200 [thread overview]
Message-ID: <b520f8c8-5ab6-79f6-7eef-28f6f14f536e@linaro.org> (raw)
In-Reply-To: <20230328193632.226095-6-brgl@bgdev.pl>
On 28.03.2023 21:36, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
>
> Add the PCIe SMMU node for sa8775p platforms.
>
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 74 +++++++++++++++++++++++++++
> 1 file changed, 74 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> index 2343df7e0ea4..9ab630c7d81b 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -809,6 +809,80 @@ apps_smmu: iommu@15000000 {
> <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> + pcie_smmu: iommu@15200000 {
> + compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
> + reg = <0x0 0x15200000 0x0 0x800000>;
> + #iommu-cells = <2>;
> + #global-interrupts = <2>;
> +
> + interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>,
That's a lot of interrupts!
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> + <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> intc: interrupt-controller@17a00000 {
> compatible = "arm,gic-v3";
> reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
next prev parent reply other threads:[~2023-03-29 11:33 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-28 19:36 [PATCH 0/7] arm64: dts: qcom: sa8775p: add more IOMMUs Bartosz Golaszewski
2023-03-28 19:36 ` [PATCH 1/7] dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P Bartosz Golaszewski
2023-03-29 8:30 ` Krzysztof Kozlowski
2023-03-28 19:36 ` [PATCH 2/7] clk: qcom: add the GPUCC driver for sa8775p Bartosz Golaszewski
2023-03-29 2:15 ` Stephen Boyd
2023-04-06 11:20 ` Bartosz Golaszewski
2023-04-10 19:09 ` Stephen Boyd
2023-03-29 11:30 ` Konrad Dybcio
2023-03-28 19:36 ` [PATCH 3/7] arm64: defconfig: enable the SA8775P GPUCC driver Bartosz Golaszewski
2023-03-29 8:33 ` Krzysztof Kozlowski
2023-04-06 13:28 ` Dmitry Baryshkov
2023-03-28 19:36 ` [PATCH 4/7] dt-bindings: iommu: arm,smmu: enable clocks for sa8775p Bartosz Golaszewski
2023-03-29 8:31 ` Krzysztof Kozlowski
2023-04-03 20:41 ` Rob Herring
2023-04-03 22:38 ` Konrad Dybcio
2023-03-28 19:36 ` [PATCH 5/7] arm64: dts: qcom: sa8775p: add the pcie smmu node Bartosz Golaszewski
2023-03-29 11:33 ` Konrad Dybcio [this message]
2023-03-28 19:36 ` [PATCH 6/7] arm64: dts: qcom: sa8775p: add the GPU clock controller node Bartosz Golaszewski
2023-03-29 11:31 ` Konrad Dybcio
2023-03-28 19:36 ` [PATCH 7/7] arm64: dts: qcom: sa8775p: add the GPU IOMMU node Bartosz Golaszewski
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