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[83.9.3.225]) by smtp.gmail.com with ESMTPSA id m18-20020a195212000000b004e95f53adc7sm5445662lfb.27.2023.03.29.04.33.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 29 Mar 2023 04:33:10 -0700 (PDT) Message-ID: Date: Wed, 29 Mar 2023 13:33:09 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 Subject: Re: [PATCH 5/7] arm64: dts: qcom: sa8775p: add the pcie smmu node Content-Language: en-US To: Bartosz Golaszewski , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Bartosz Golaszewski References: <20230328193632.226095-1-brgl@bgdev.pl> <20230328193632.226095-6-brgl@bgdev.pl> From: Konrad Dybcio In-Reply-To: <20230328193632.226095-6-brgl@bgdev.pl> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 28.03.2023 21:36, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski > > Add the PCIe SMMU node for sa8775p platforms. > > Signed-off-by: Bartosz Golaszewski > --- > arch/arm64/boot/dts/qcom/sa8775p.dtsi | 74 +++++++++++++++++++++++++++ > 1 file changed, 74 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > index 2343df7e0ea4..9ab630c7d81b 100644 > --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi > +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > @@ -809,6 +809,80 @@ apps_smmu: iommu@15000000 { > ; > }; > > + pcie_smmu: iommu@15200000 { > + compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; > + reg = <0x0 0x15200000 0x0 0x800000>; > + #iommu-cells = <2>; > + #global-interrupts = <2>; > + > + interrupts = , > + , That's a lot of interrupts! Reviewed-by: Konrad Dybcio Konrad > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + }; > + > intc: interrupt-controller@17a00000 { > compatible = "arm,gic-v3"; > reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */