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[178.235.177.23]) by smtp.gmail.com with ESMTPSA id n19-20020a170906165300b009a1c05bd672sm7949359ejd.127.2023.09.26.10.29.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 26 Sep 2023 10:29:32 -0700 (PDT) Message-ID: Date: Tue, 26 Sep 2023 19:29:30 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V1 2/2] arm64: dts: qcom: sc7280: Add UFS host controller and phy nodes To: Nitin Rawat , Manivannan Sadhasivam Cc: agross@kernel.org, andersson@kernel.org, alim.akhtar@samsung.com, bvanassche@acm.org, robh+dt@kernel.org, avri.altman@wdc.com, cros-qcom-dts-watchers@chromium.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20230821094937.13059-1-quic_nitirawa@quicinc.com> <20230821094937.13059-3-quic_nitirawa@quicinc.com> <20230822070841.GA24753@thinkpad> <593fa9be-9f55-3649-e825-1dee31ac5c21@quicinc.com> Content-Language: en-US From: Konrad Dybcio Autocrypt: addr=konrad.dybcio@linaro.org; keydata= xsFNBF9ALYUBEADWAhxdTBWrwAgDQQzc1O/bJ5O7b6cXYxwbBd9xKP7MICh5YA0DcCjJSOum BB/OmIWU6X+LZW6P88ZmHe+KeyABLMP5s1tJNK1j4ntT7mECcWZDzafPWF4F6m4WJOG27kTJ HGWdmtO+RvadOVi6CoUDqALsmfS3MUG5Pj2Ne9+0jRg4hEnB92AyF9rW2G3qisFcwPgvatt7 TXD5E38mLyOPOUyXNj9XpDbt1hNwKQfiidmPh5e7VNAWRnW1iCMMoKqzM1Anzq7e5Afyeifz zRcQPLaqrPjnKqZGL2BKQSZDh6NkI5ZLRhhHQf61fkWcUpTp1oDC6jWVfT7hwRVIQLrrNj9G MpPzrlN4YuAqKeIer1FMt8cq64ifgTzxHzXsMcUdclzq2LTk2RXaPl6Jg/IXWqUClJHbamSk t1bfif3SnmhA6TiNvEpDKPiT3IDs42THU6ygslrBxyROQPWLI9IL1y8S6RtEh8H+NZQWZNzm UQ3imZirlPjxZtvz1BtnnBWS06e7x/UEAguj7VHCuymVgpl2Za17d1jj81YN5Rp5L9GXxkV1 aUEwONM3eCI3qcYm5JNc5X+JthZOWsbIPSC1Rhxz3JmWIwP1udr5E3oNRe9u2LIEq+wH/toH kpPDhTeMkvt4KfE5m5ercid9+ZXAqoaYLUL4HCEw+HW0DXcKDwARAQABzShLb25yYWQgRHli Y2lvIDxrb25yYWQuZHliY2lvQGxpbmFyby5vcmc+wsGOBBMBCAA4FiEEU24if9oCL2zdAAQV R4cBcg5dfFgFAmQ5bqwCGwMFCwkIBwIGFQoJCAsCBBYCAwECHgECF4AACgkQR4cBcg5dfFjO BQ//YQV6fkbqQCceYebGg6TiisWCy8LG77zV7DB0VMIWJv7Km7Sz0QQrHQVzhEr3trNenZrf yy+o2tQOF2biICzbLM8oyQPY8B///KJTWI2khoB8IJSJq3kNG68NjPg2vkP6CMltC/X3ohAo xL2UgwN5vj74QnlNneOjc0vGbtA7zURNhTz5P/YuTudCqcAbxJkbqZM4WymjQhe0XgwHLkiH 5LHSZ31MRKp/+4Kqs4DTXMctc7vFhtUdmatAExDKw8oEz5NbskKbW+qHjW1XUcUIrxRr667V GWH6MkVceT9ZBrtLoSzMLYaQXvi3sSAup0qiJiBYszc/VOu3RbIpNLRcXN3KYuxdQAptacTE mA+5+4Y4DfC3rUSun+hWLDeac9z9jjHm5rE998OqZnOU9aztbd6zQG5VL6EKgsVXAZD4D3RP x1NaAjdA3MD06eyvbOWiA5NSzIcC8UIQvgx09xm7dThCuQYJR4Yxjd+9JPJHI6apzNZpDGvQ BBZzvwxV6L1CojUEpnilmMG1ZOTstktWpNzw3G2Gis0XihDUef0MWVsQYJAl0wfiv/0By+XK mm2zRR+l/dnzxnlbgJ5pO0imC2w0TVxLkAp0eo0LHw619finad2u6UPQAkZ4oj++iIGrJkt5 Lkn2XgB+IW8ESflz6nDY3b5KQRF8Z6XLP0+IEdLOOARkOW7yEgorBgEEAZdVAQUBAQdAwmUx xrbSCx2ksDxz7rFFGX1KmTkdRtcgC6F3NfuNYkYDAQgHwsF2BBgBCAAgFiEEU24if9oCL2zd AAQVR4cBcg5dfFgFAmQ5bvICGwwACgkQR4cBcg5dfFju1Q//Xta1ShwL0MLSC1KL1lXGXeRM 8arzfyiB5wJ9tb9U/nZvhhdfilEDLe0jKJY0RJErbdRHsalwQCrtq/1ewQpMpsRxXzAjgfRN jc4tgxRWmI+aVTzSRpywNahzZBT695hMz81cVZJoZzaV0KaMTlSnBkrviPz1nIGHYCHJxF9r cIu0GSIyUjZ/7xslxdvjpLth16H27JCWDzDqIQMtg61063gNyEyWgt1qRSaK14JIH/DoYRfn jfFQSC8bffFjat7BQGFz4ZpRavkMUFuDirn5Tf28oc5ebe2cIHp4/kajTx/7JOxWZ80U70mA cBgEeYSrYYnX+UJsSxpzLc/0sT1eRJDEhI4XIQM4ClIzpsCIN5HnVF76UQXh3a9zpwh3dk8i bhN/URmCOTH+LHNJYN/MxY8wuukq877DWB7k86pBs5IDLAXmW8v3gIDWyIcgYqb2v8QO2Mqx YMqL7UZxVLul4/JbllsQB8F/fNI8AfttmAQL9cwo6C8yDTXKdho920W4WUR9k8NT/OBqWSyk bGqMHex48FVZhexNPYOd58EY9/7mL5u0sJmo+jTeb4JBgIbFPJCFyng4HwbniWgQJZ1WqaUC nas9J77uICis2WH7N8Bs9jy0wQYezNzqS+FxoNXmDQg2jetX8en4bO2Di7Pmx0jXA4TOb9TM izWDgYvmBE8= In-Reply-To: <593fa9be-9f55-3649-e825-1dee31ac5c21@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net On 26.09.2023 18:24, Nitin Rawat wrote: > > > On 8/22/2023 12:38 PM, Manivannan Sadhasivam wrote: >> On Mon, Aug 21, 2023 at 03:19:37PM +0530, Nitin Rawat wrote: >>> Add UFS host controller and PHY nodes for sc7280. >>> >> >> You should split this patch into 2. One for SoC and another for board. > Updated in Latest Patchset. > >> >>> Signed-off-by: Nitin Rawat >>> --- >>>   arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 19 +++++++ >>>   arch/arm64/boot/dts/qcom/sc7280.dtsi     | 64 ++++++++++++++++++++++++ >>>   2 files changed, 83 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi >>> index 2ff549f4dc7a..c60cdd511222 100644 >>> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi >>> @@ -451,6 +451,25 @@ >>>       status = "okay"; >>>   }; >>> >>> +&ufs_mem_hc { >>> +    reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; >>> +    vcc-supply = <&vreg_l7b_2p9>; >>> +    vcc-max-microamp = <800000>; >>> +    vccq-supply = <&vreg_l9b_1p2>; >>> +    vccq-max-microamp = <900000>; >>> +    vccq2-supply = <&vreg_l9b_1p2>; >>> +    vccq2-max-microamp = <900000>; >>> + >>> +    status = "okay"; >>> +}; >>> + >>> +&ufs_mem_phy { >>> +    vdda-phy-supply = <&vreg_l10c_0p8>; >>> +    vdda-pll-supply = <&vreg_l6b_1p2>; >>> + >>> +    status = "okay"; >>> +}; >>> + >>>   &sdhc_1 { >>>       status = "okay"; >>> >>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi >>> index 925428a5f6ae..d4a15d56b384 100644 >>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >>> @@ -908,6 +908,70 @@ >>>               }; >>>           }; >>> >>> +        ufs_mem_phy: phy@1d87000 { >> >> Please sort the nodes in ascending order. > Updated in Latest Patchset. > >> >>> +            compatible = "qcom,sc7280-qmp-ufs-phy"; >>> +            reg = <0x0 0x01d87000 0x0 0xe00>; >>> +            clocks = <&rpmhcc RPMH_CXO_CLK>, >>> +                 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, >>> +                 <&gcc GCC_UFS_1_CLKREF_EN>; >>> +            clock-names = "ref", "ref_aux", "qref"; >>> + >>> +            resets = <&ufs_mem_hc 0>; >>> +            reset-names = "ufsphy"; >>> + >>> +            #clock-cells = <1>; >>> +            #phy-cells = <0>; >>> + >>> +            status = "disabled"; >>> + >>> +        }; >>> + >>> +        ufs_mem_hc: ufs@1d84000 { >>> +            compatible = "qcom,sc7280-ufshc", "qcom,ufshc", >>> +                     "jedec,ufs-2.0"; >>> +            reg = <0x0 0x01d84000 0x0 0x3000>; >>> +            interrupts = ; >>> +            phys = <&ufs_mem_phy>; >>> +            phy-names = "ufsphy"; >>> +            lanes-per-direction = <2>; >>> +            #reset-cells = <1>; >>> +            resets = <&gcc GCC_UFS_PHY_BCR>; >>> +            reset-names = "rst"; >>> + >>> +            power-domains = <&gcc GCC_UFS_PHY_GDSC>; >>> +            required-opps = <&rpmhpd_opp_nom>; >>> + >>> +            iommus = <&apps_smmu 0x80 0x0>; >>> +            dma-coherent; >>> + >>> +            clock-names = "core_clk", >>> +                      "bus_aggr_clk", >>> +                      "iface_clk", >>> +                      "core_clk_unipro", >>> +                      "ref_clk", >>> +                      "tx_lane0_sync_clk", >>> +                      "rx_lane0_sync_clk", >>> +                      "rx_lane1_sync_clk"; >> >> "clocks" property should come first. >  DT binding shows clock-names first followed by clocks. >  Let me know if see still see concern, would update . The dt bindings example is rarely useful.. perhaps we should change that.. The general consensus there is to have property property-names Konrad