From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C3E7C433F5 for ; Wed, 6 Oct 2021 07:39:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 80F536115A for ; Wed, 6 Oct 2021 07:39:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237335AbhJFHlI (ORCPT ); Wed, 6 Oct 2021 03:41:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54940 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230013AbhJFHlH (ORCPT ); Wed, 6 Oct 2021 03:41:07 -0400 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 34226C061749 for ; Wed, 6 Oct 2021 00:39:16 -0700 (PDT) Received: from gallifrey.ext.pengutronix.de ([2001:67c:670:201:5054:ff:fe8d:eefb] helo=[IPv6:::1]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1mY1W9-0000li-VC; Wed, 06 Oct 2021 09:39:10 +0200 Message-ID: Subject: Re: [PATCH 2/7] dt-bindings: soc: add binding for i.MX8MN DISP blk-ctrl From: Lucas Stach To: Adam Ford , linux-arm-kernel@lists.infradead.org Cc: aford@beaconembedded.com, Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Date: Wed, 06 Oct 2021 09:39:08 +0200 In-Reply-To: <20211006000505.627334-2-aford173@gmail.com> References: <20211006000505.627334-1-aford173@gmail.com> <20211006000505.627334-2-aford173@gmail.com> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.40.4 (3.40.4-1.fc34) MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-SA-Exim-Connect-IP: 2001:67c:670:201:5054:ff:fe8d:eefb X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: devicetree@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Am Dienstag, dem 05.10.2021 um 19:04 -0500 schrieb Adam Ford: > This adds the DT binding for the i.MX8MN DISP blk-ctrl. > > Signed-off-by: Adam Ford > --- > .../soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml | 97 +++++++++++++++++++ > 1 file changed, 97 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml > > diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml > new file mode 100644 > index 000000000000..92d30aff446e > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml > @@ -0,0 +1,97 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml# mm -> mn in the file name. > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NXP i.MX8MN DISP blk-ctrl > + > +maintainers: > + - Lucas Stach I'm not opposed to being maintainer for this file, just making sure that this is what you intended. Other than that I think this looks okay. Regards, Lucas > + > +description: > + The i.MX8MN DISP blk-ctrl is a top-level peripheral providing access to > + the NoC and ensuring proper power sequencing of the display and MIPI CSI > + peripherals located in the DISP domain of the SoC. > + > +properties: > + compatible: > + items: > + - const: fsl,imx8mn-disp-blk-ctrl > + - const: syscon > + > + reg: > + maxItems: 1 > + > + '#power-domain-cells': > + const: 1 > + > + power-domains: > + minItems: 5 > + maxItems: 5 > + > + power-domain-names: > + items: > + - const: bus > + - const: isi > + - const: lcdif > + - const: mipi-dsi > + - const: mipi-csi > + > + clocks: > + minItems: 11 > + maxItems: 11 > + > + clock-names: > + items: > + - const: disp_axi > + - const: disp_apb > + - const: disp_axi_root > + - const: disp_apb_root > + - const: lcdif-axi > + - const: lcdif-apb > + - const: lcdif-pix > + - const: dsi-pclk > + - const: dsi-ref > + - const: csi-aclk > + - const: csi-pclk > + > +required: > + - compatible > + - reg > + - power-domains > + - power-domain-names > + - clocks > + - clock-names > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + > + disp_blk_ctl: blk_ctrl@32e28000 { > + compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon"; > + reg = <0x32e28000 0x100>; > + power-domains = <&pgc_dispmix>, <&pgc_dispmix>, > + <&pgc_dispmix>, <&pgc_mipi>, > + <&pgc_mipi>; > + power-domain-names = "bus", "isi", "lcdif", "mipi-dsi", > + "mipi-csi"; > + clocks = <&clk IMX8MN_CLK_DISP_AXI>, > + <&clk IMX8MN_CLK_DISP_APB>, > + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, > + <&clk IMX8MN_CLK_DISP_APB_ROOT>, > + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, > + <&clk IMX8MN_CLK_DISP_APB_ROOT>, > + <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, > + <&clk IMX8MN_CLK_DSI_CORE>, > + <&clk IMX8MN_CLK_DSI_PHY_REF>, > + <&clk IMX8MN_CLK_CSI1_PHY_REF>, > + <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>; > + clock-names = "disp_axi", "disp_apb", "disp_axi_root", "disp_apb_root", > + "lcdif-axi", "lcdif-apb", "lcdif-pix", "dsi-pclk", > + "dsi-ref", "csi-aclk", "csi-pclk"; > + #power-domain-cells = <1>; > + };