From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dmitry Osipenko Subject: Re: [PATCH v1 4/5] dmaengine: Add driver for NVIDIA Tegra AHB DMA controller Date: Thu, 28 Sep 2017 17:06:03 +0300 Message-ID: References: <0a45e058baba72124b91c663ce1d908d275f4044.1506380746.git.digetx@gmail.com> <20170928092949.GB30097@localhost> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20170928092949.GB30097@localhost> Content-Language: en-US Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Vinod Koul Cc: Thierry Reding , Jonathan Hunter , Laxman Dewangan , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Rob Herring , linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, dmaengine-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: devicetree@vger.kernel.org On 28.09.2017 12:29, Vinod Koul wrote: >> + default: >> + return -EINVAL; >> + } >> + >> + ahb_seq = burst << TEGRA_AHBDMA_CHANNEL_AHB_BURST_SHIFT; >> + ahb_seq |= TEGRA_AHBDMA_CHANNEL_ADDR_WRAP; >> + ahb_seq |= TEGRA_AHBDMA_CHANNEL_INTR_ENB; >> + >> + writel_relaxed(ahb_seq, >> + ahbdma_chan->regs + TEGRA_AHBDMA_CHANNEL_AHB_SEQ); >> + >> + writel_relaxed(ahb_addr, >> + ahbdma_chan->regs + TEGRA_AHBDMA_CHANNEL_AHB_PTR); > > oh no, you don't write to HW here. This can be called anytime when you have > txn running! You should save these and use them in prep_ calls. > BTW, some of the DMA drivers have exactly the same problem. I now see that it is actually documented explicitly in provider.txt, but that's inconsistent across the actual drivers. -- Dmitry