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Thu, 10 Sep 2020 03:44:14 -0700 (PDT) Subject: Re: [PATCH v5 2/4] PCI: mediatek: Use regmap to get shared pcie-cfg base To: Chuanjia Liu , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi Cc: devicetree@vger.kernel.org, Ryder Lee , Frank Wunderlich , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, yong.wu@mediatek.com References: <20200910061115.909-1-chuanjia.liu@mediatek.com> <20200910061115.909-3-chuanjia.liu@mediatek.com> From: Matthias Brugger Message-ID: Date: Thu, 10 Sep 2020 12:44:08 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 MIME-Version: 1.0 In-Reply-To: <20200910061115.909-3-chuanjia.liu@mediatek.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 10/09/2020 08:11, Chuanjia Liu wrote: > Use regmap to get shared pcie-cfg base and change > the method to get pcie irq. > > Acked-by: Ryder Lee > Signed-off-by: Chuanjia Liu > --- > drivers/pci/controller/pcie-mediatek.c | 25 ++++++++++++++++++------- > 1 file changed, 18 insertions(+), 7 deletions(-) > > diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c > index cf4c18f0c25a..987845d19982 100644 > --- a/drivers/pci/controller/pcie-mediatek.c > +++ b/drivers/pci/controller/pcie-mediatek.c > @@ -14,6 +14,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -23,6 +24,7 @@ > #include > #include > #include > +#include > #include > > #include "../pci.h" > @@ -205,6 +207,7 @@ struct mtk_pcie_port { > * struct mtk_pcie - PCIe host information > * @dev: pointer to PCIe device > * @base: IO mapped register base > + * @cfg: IO mapped register map for PCIe config > * @free_ck: free-run reference clock > * @mem: non-prefetchable memory resource > * @ports: pointer to PCIe port information > @@ -213,6 +216,7 @@ struct mtk_pcie_port { > struct mtk_pcie { > struct device *dev; > void __iomem *base; > + struct regmap *cfg; > struct clk *free_ck; > > struct list_head ports; > @@ -648,7 +652,7 @@ static int mtk_pcie_setup_irq(struct mtk_pcie_port *port, > return err; > } > > - port->irq = platform_get_irq(pdev, port->slot); > + port->irq = platform_get_irq_byname(pdev, "pcie_irq"); > if (port->irq < 0) > return port->irq; You will need to make sure taht the driver keeps working with the old DTS format. This is not the case here. Regards, Matthias > > @@ -674,12 +678,11 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) > if (!mem) > return -EINVAL; > > - /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */ > - if (pcie->base) { > - val = readl(pcie->base + PCIE_SYS_CFG_V2); > - val |= PCIE_CSR_LTSSM_EN(port->slot) | > - PCIE_CSR_ASPM_L1_EN(port->slot); > - writel(val, pcie->base + PCIE_SYS_CFG_V2); > + /* MT7622/MT7629 platforms need to enable LTSSM and ASPM. */ > + if (pcie->cfg) { > + val = PCIE_CSR_LTSSM_EN(port->slot) | > + PCIE_CSR_ASPM_L1_EN(port->slot); > + regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val); > } > > /* Assert all reset signals */ > @@ -983,6 +986,7 @@ static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie) > struct device *dev = pcie->dev; > struct platform_device *pdev = to_platform_device(dev); > struct resource *regs; > + struct device_node *cfg_node; > int err; > > /* get shared registers, which are optional */ > @@ -995,6 +999,13 @@ static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie) > } > } > > + cfg_node = of_parse_phandle(dev->of_node, "mediatek,pcie-cfg", 0); > + if (cfg_node) { > + pcie->cfg = syscon_node_to_regmap(cfg_node); > + if (IS_ERR(pcie->cfg)) > + return PTR_ERR(pcie->cfg); > + } > + > pcie->free_ck = devm_clk_get(dev, "free_ck"); > if (IS_ERR(pcie->free_ck)) { > if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER) >