From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A91D22EF67F; Tue, 17 Jun 2025 14:49:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750171753; cv=none; b=TSpgm/AOOeB0CXRnoT7pwdrTh4KAxyhsH5VOOh1Y/ejTvQdTtOxUbpeyXqRdj50oHZtHu9l7Vy2pm0tW4h6i2PIEj1brYEF/Ro7vQvIIFtG7I+frkEL2JpD8oMIZxmJI9Epxf2V4iDrT3GZk0ArLkG6V0aCTU9yVZgDCgORPq5Q= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750171753; c=relaxed/simple; bh=yjfeWd+qMjJg4DXW0gYXbgQDgaHC4orhH4SkwKt42Qk=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=cVrV1MqpvVp5QfGNiD2dOs1xWDzT6dirzCDj41FM2Gch4uE62ethTwMvGFPqILNYOuU4kFfu/xdp8iD5yL5jeCY5HGy6nWT2Mni3O0Y1sZmNoozx2CYTaTSxYWYuefO19Pvd+QsPHJzok6xArp18/PhtJlwbim2hYIhu87qG0JM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=a5ObIMYQ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="a5ObIMYQ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6150AC4CEE7; Tue, 17 Jun 2025 14:49:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750171753; bh=yjfeWd+qMjJg4DXW0gYXbgQDgaHC4orhH4SkwKt42Qk=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=a5ObIMYQ7s0FIoj0USZ4e4Ld4Jy4XRa4PEIbuudixRcKRsPzBnxx87xznDxmMVoOA IfEf3v36Srg1cceWQ55ag6ElgrLli+4qlDvQlsTyUdziY21J0hOZyk58TlFxWLFlK1 1SEc6i2J6habr3wDMg6T084IWvQrHjcz0jy429NjipZxtHd8X5byTmJBbFXIvZ04QZ VQo04f4g3rlef6XtejtHxy3H9MTZjvlaW9v0Fq0e6WXA0LIyJUK5BZnv7SjXafwjjX 20kaxu4CEbwjjvUV/w2lLS20S1zGiU2i2/BzQW9tmL5RXbCGEH2DRhgj52MCB1HS0p evHhovKdTZVZg== Message-ID: Date: Tue, 17 Jun 2025 16:49:05 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 5/8] dt-bindings: clock: qcom: Add NSS clock controller for IPQ5424 SoC To: Luo Jie , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Michael Turquette , Stephen Boyd , Philipp Zabel , Anusha Rao , Richard Cochran , Konrad Dybcio , Catalin Marinas , Will Deacon Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com, quic_pavir@quicinc.com References: <20250617-qcom_ipq5424_nsscc-v1-0-4dc2d6b3cdfc@quicinc.com> <20250617-qcom_ipq5424_nsscc-v1-5-4dc2d6b3cdfc@quicinc.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 17/06/2025 14:06, Luo Jie wrote: > NSS clock controller provides the clocks and resets to the > networking blocks such as PPE (Packet Process Engine) and > UNIPHY (PCS) on IPQ5424 devices. Please wrap commit message according to Linux coding style / submission process (neither too early nor over the limit): https://elixir.bootlin.com/linux/v6.4-rc1/source/Documentation/process/submitting-patches.rst#L597 > > Add the compatible "qcom,ipq5424-nsscc" support based on the > current IPQ9574 NSS clock controller DT binding file. > ICC clocks are always provided by the NSS clock controller > of IPQ9574 and IPQ5424, so add interconnect-cells as required > DT property. > > Also add master/slave ids for IPQ5424 networking interfaces, > which is used by nss-ipq5424 driver for providing interconnect > services using icc-clk framework. > > Signed-off-by: Luo Jie > --- > .../bindings/clock/qcom,ipq9574-nsscc.yaml | 66 +++++++++++++++++++--- > include/dt-bindings/clock/qcom,ipq5424-nsscc.h | 65 +++++++++++++++++++++ > include/dt-bindings/interconnect/qcom,ipq5424.h | 13 +++++ > include/dt-bindings/reset/qcom,ipq5424-nsscc.h | 46 +++++++++++++++ > 4 files changed, 182 insertions(+), 8 deletions(-) > > diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml > index 17252b6ea3be..5bc2fe049b26 100644 > --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml > +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml > @@ -4,7 +4,7 @@ > $id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml# > $schema: http://devicetree.org/meta-schemas/core.yaml# > > -title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 > +title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 and IPQ5424 > > maintainers: > - Bjorn Andersson > @@ -12,21 +12,25 @@ maintainers: > > description: | > Qualcomm networking sub system clock control module provides the clocks, > - resets on IPQ9574 > + resets on IPQ9574 and IPQ5424 > > - See also:: > + See also: > + include/dt-bindings/clock/qcom,ipq5424-nsscc.h > include/dt-bindings/clock/qcom,ipq9574-nsscc.h > + include/dt-bindings/reset/qcom,ipq5424-nsscc.h > include/dt-bindings/reset/qcom,ipq9574-nsscc.h > > properties: > compatible: > - const: qcom,ipq9574-nsscc > + enum: > + - qcom,ipq5424-nsscc > + - qcom,ipq9574-nsscc > > clocks: > items: > - description: Board XO source > - - description: CMN_PLL NSS 1200MHz (Bias PLL cc) clock source > - - description: CMN_PLL PPE 353MHz (Bias PLL ubi nc) clock source > + - description: CMN_PLL NSS 1200 MHz or 300 MHZ (Bias PLL cc) clock source > + - description: CMN_PLL PPE 353 MHz or 375 MHZ (Bias PLL ubi nc) clock source This change means devices are different. Just ocme with your own schema. Best regards, Krzysztof