From: Xingyu Wu <xingyu.wu@starfivetech.com>
To: Conor Dooley <conor@kernel.org>
Cc: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
"Michael Turquette" <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
"Rob Herring" <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Emil Renner Berthing <emil.renner.berthing@canonical.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Hal Feng <hal.feng@starfivetech.com>,
William Qiu <william.qiu@starfivetech.com>,
<linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>
Subject: Re: [RESEND PATCH v6 3/7] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs
Date: Fri, 7 Jul 2023 15:45:45 +0800 [thread overview]
Message-ID: <b649773b-ec51-20fa-a5a1-553e89b0d223@starfivetech.com> (raw)
In-Reply-To: <20230704-tingling-automaker-22460e884793@spud>
On 2023/7/5 6:23, Conor Dooley wrote:
> On Tue, Jul 04, 2023 at 02:46:06PM +0800, Xingyu Wu wrote:
>> Add PLL clock inputs from PLL clock generator.
>>
>> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
>
> As expected this produces warnings for the existing, in-tree,
> devicetrees which go away when the later dts patches are applied.
> It'd be good to mention that its intentional if you end up sending
> another version of the series.
>
> Otherwise, this looks good to me too.
>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>
Thanks, I will add the mentions in next version.
Best regards,
Xingyu Wu
next prev parent reply other threads:[~2023-07-07 7:49 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-04 6:46 [RESEND PATCH v6 0/7] Add PLL clocks driver and syscon for StarFive JH7110 SoC Xingyu Wu
2023-07-04 6:46 ` [RESEND PATCH v6 1/7] dt-bindings: clock: Add StarFive JH7110 PLL clock generator Xingyu Wu
2023-07-13 12:26 ` Emil Renner Berthing
2023-07-14 6:24 ` Xingyu Wu
2023-07-04 6:46 ` [RESEND PATCH v6 2/7] dt-bindings: soc: starfive: Add StarFive syscon module Xingyu Wu
2023-07-04 22:21 ` Conor Dooley
2023-07-05 6:29 ` Krzysztof Kozlowski
2023-07-13 12:31 ` Emil Renner Berthing
2023-07-04 6:46 ` [RESEND PATCH v6 3/7] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs Xingyu Wu
2023-07-04 22:23 ` Conor Dooley
2023-07-07 7:45 ` Xingyu Wu [this message]
2023-07-13 12:34 ` Emil Renner Berthing
2023-07-04 6:46 ` [RESEND PATCH v6 4/7] clk: starfive: Add StarFive JH7110 PLL clock driver Xingyu Wu
2023-07-13 12:37 ` Emil Renner Berthing
2023-07-04 6:46 ` [RESEND PATCH v6 5/7] clk: starfive: jh7110-sys: Add PLL clocks source from DTS Xingyu Wu
2023-07-04 22:25 ` Conor Dooley
2023-07-12 3:24 ` Hal Feng
2023-07-13 13:15 ` Emil Renner Berthing
2023-07-14 8:01 ` Xingyu Wu
2023-07-14 9:36 ` Emil Renner Berthing
2023-07-04 6:46 ` [RESEND PATCH v6 6/7] riscv: dts: starfive: jh7110: Add syscon nodes Xingyu Wu
2023-07-13 13:21 ` Emil Renner Berthing
2023-07-04 6:46 ` [RESEND PATCH v6 7/7] riscv: dts: starfive: jh7110: Add PLL clocks source in SYSCRG node Xingyu Wu
2023-07-13 13:24 ` Emil Renner Berthing
2023-07-04 22:29 ` [RESEND PATCH v6 0/7] Add PLL clocks driver and syscon for StarFive JH7110 SoC Conor Dooley
2023-07-12 16:09 ` Conor Dooley
2023-07-05 6:27 ` Krzysztof Kozlowski
2023-07-07 7:41 ` Xingyu Wu
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