* [PATCH v1 0/2] dts: aspeed: greatlakes: Update Greatlakes devicetree
@ 2023-03-29 8:32 Delphine CC Chiu
2023-03-29 8:32 ` [PATCH v1 1/2] ARM: dts: aspeed: greatlakes: Add gpio names Delphine CC Chiu
2023-03-29 8:32 ` [PATCH v1 2/2] ARM: dts: aspeed: greatlakes: add mctp device Delphine CC Chiu
0 siblings, 2 replies; 7+ messages in thread
From: Delphine CC Chiu @ 2023-03-29 8:32 UTC (permalink / raw)
To: patrick
Cc: Delphine CC Chiu, Rob Herring, Krzysztof Kozlowski, Joel Stanley,
Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
v1 - Update Greatlakes BMC devicetree
Delphine CC Chiu (2):
ARM: dts: aspeed: greatlakes: Add gpio names
ARM: dts: aspeed: greatlakes: add mctp device
.../dts/aspeed-bmc-facebook-greatlakes.dts | 54 +++++++++++++++++++
1 file changed, 54 insertions(+)
--
2.17.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v1 1/2] ARM: dts: aspeed: greatlakes: Add gpio names
2023-03-29 8:32 [PATCH v1 0/2] dts: aspeed: greatlakes: Update Greatlakes devicetree Delphine CC Chiu
@ 2023-03-29 8:32 ` Delphine CC Chiu
2023-03-29 8:36 ` Krzysztof Kozlowski
2023-03-29 8:32 ` [PATCH v1 2/2] ARM: dts: aspeed: greatlakes: add mctp device Delphine CC Chiu
1 sibling, 1 reply; 7+ messages in thread
From: Delphine CC Chiu @ 2023-03-29 8:32 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Joel Stanley,
Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
From: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
Add GPIO names for SOC lines.
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../dts/aspeed-bmc-facebook-greatlakes.dts | 49 +++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
index 8c05bd56ce1e..59819115c39d 100644
--- a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
@@ -238,4 +238,53 @@
&gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpiu1_default &pinctrl_gpiu7_default>;
+ status = "okay";
+ gpio-line-names =
+ /*A0-A7*/ "","","","","","","","",
+ /*B0-B7*/ "power-bmc-nic","presence-ocp-debug",
+ "power-bmc-slot1","power-bmc-slot2",
+ "power-bmc-slot3","power-bmc-slot4","","",
+ /*C0-C7*/ "presence-ocp-nic","","","reset-cause-nic-primary",
+ "reset-cause-nic-secondary","","","",
+ /*D0-D7*/ "","","","","","","","",
+ /*E0-E7*/ "","","","","","","","",
+ /*F0-F7*/ "slot1-bmc-reset-button","slot2-bmc-reset-button",
+ "slot3-bmc-reset-button","slot4-bmc-reset-button",
+ "","","","presence-emmc",
+ /*G0-G7*/ "","","","","","","","",
+ /*H0-H7*/ "","","","",
+ "presence-mb-slot1","presence-mb-slot2",
+ "presence-mb-slot3","presence-mb-slot4",
+ /*I0-I7*/ "","","","","","","bb-bmc-button","",
+ /*J0-J7*/ "","","","","","","","",
+ /*K0-K7*/ "","","","","","","","",
+ /*L0-L7*/ "","","","","","","","",
+ /*M0-M7*/ "","power-nic-bmc-enable","","usb-bmc-enable","","reset-cause-usb-hub","","",
+ /*N0-N7*/ "","","","","bmc-ready","","","",
+ /*O0-O7*/ "","","","","","","fan0-bmc-cpld-enable","fan1-bmc-cpld-enable",
+ /*P0-P7*/ "fan2-bmc-cpld-enable","fan3-bmc-cpld-enable",
+ "reset-cause-pcie-slot1","reset-cause-pcie-slot2",
+ "reset-cause-pcie-slot3","reset-cause-pcie-slot4","","",
+ /*Q0-Q7*/ "","","","","","","","",
+ /*R0-R7*/ "","","","","","","","",
+ /*S0-S7*/ "","","power-p5v-usb","presence-bmc-tpm","","","","",
+ /*T0-T7*/ "","","","","","","","",
+ /*U0-U7*/ "","","","","","","","GND",
+ /*V0-V7*/ "bmc-slot1-ac-button","bmc-slot2-ac-button",
+ "bmc-slot3-ac-button","bmc-slot4-ac-button",
+ "","","","",
+ /*W0-W7*/ "","","","","","","","",
+ /*X0-X7*/ "","","","","","","","",
+ /*Y0-Y7*/ "","","","reset-cause-emmc","","","","",
+ /*Z0-Z7*/ "","","","","","","","";
+};
+
+&gpio1 {
+ status = "okay";
+ gpio-line-names =
+ /*18A0-18A7*/ "","","","","","","","",
+ /*18B0-18B7*/ "","","","","","","","",
+ /*18C0-18C7*/ "","","","","","","","",
+ /*18D0-18D7*/ "","","","","","","","",
+ /*18E0-18E3*/ "","","","","","","","";
};
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v1 2/2] ARM: dts: aspeed: greatlakes: add mctp device
2023-03-29 8:32 [PATCH v1 0/2] dts: aspeed: greatlakes: Update Greatlakes devicetree Delphine CC Chiu
2023-03-29 8:32 ` [PATCH v1 1/2] ARM: dts: aspeed: greatlakes: Add gpio names Delphine CC Chiu
@ 2023-03-29 8:32 ` Delphine CC Chiu
1 sibling, 0 replies; 7+ messages in thread
From: Delphine CC Chiu @ 2023-03-29 8:32 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Joel Stanley,
Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Add mctp node on I2C bus
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@Wiwynn.com>
---
arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
index 59819115c39d..2f83693e4f85 100644
--- a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
@@ -156,6 +156,7 @@
&i2c8 {
status = "okay";
+ mctp-controller;
temperature-sensor@1f {
compatible = "ti,tmp421";
reg = <0x1f>;
@@ -165,6 +166,10 @@
compatible = "st,24c32";
reg = <0x50>;
};
+ mctp@10 {
+ compatible = "mctp-i2c-controller";
+ reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
+ };
};
&i2c9 {
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v1 1/2] ARM: dts: aspeed: greatlakes: Add gpio names
2023-03-29 8:32 ` [PATCH v1 1/2] ARM: dts: aspeed: greatlakes: Add gpio names Delphine CC Chiu
@ 2023-03-29 8:36 ` Krzysztof Kozlowski
2023-04-10 7:11 ` Delphine_CC_Chiu/WYHQ/Wiwynn
0 siblings, 1 reply; 7+ messages in thread
From: Krzysztof Kozlowski @ 2023-03-29 8:36 UTC (permalink / raw)
To: Delphine CC Chiu, patrick, Rob Herring, Krzysztof Kozlowski,
Joel Stanley, Andrew Jeffery
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel
On 29/03/2023 10:32, Delphine CC Chiu wrote:
> From: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
>
> Add GPIO names for SOC lines.
>
> Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
> ---
> .../dts/aspeed-bmc-facebook-greatlakes.dts | 49 +++++++++++++++++++
> 1 file changed, 49 insertions(+)
>
> diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
> index 8c05bd56ce1e..59819115c39d 100644
> --- a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
> +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
> @@ -238,4 +238,53 @@
> &gpio0 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_gpiu1_default &pinctrl_gpiu7_default>;
> + status = "okay";
Was it disabled before?
> + gpio-line-names =
> + /*A0-A7*/ "","","","","","","","",
> + /*B0-B7*/ "power-bmc-nic","presence-ocp-debug",
> + "power-bmc-slot1","power-bmc-slot2",
> + "power-bmc-slot3","power-bmc-slot4","","",
> + /*C0-C7*/ "presence-ocp-nic","","","reset-cause-nic-primary",
> + "reset-cause-nic-secondary","","","",
> + /*D0-D7*/ "","","","","","","","",
> + /*E0-E7*/ "","","","","","","","",
> + /*F0-F7*/ "slot1-bmc-reset-button","slot2-bmc-reset-button",
> + "slot3-bmc-reset-button","slot4-bmc-reset-button",
> + "","","","presence-emmc",
> + /*G0-G7*/ "","","","","","","","",
> + /*H0-H7*/ "","","","",
> + "presence-mb-slot1","presence-mb-slot2",
> + "presence-mb-slot3","presence-mb-slot4",
> + /*I0-I7*/ "","","","","","","bb-bmc-button","",
> + /*J0-J7*/ "","","","","","","","",
> + /*K0-K7*/ "","","","","","","","",
> + /*L0-L7*/ "","","","","","","","",
> + /*M0-M7*/ "","power-nic-bmc-enable","","usb-bmc-enable","","reset-cause-usb-hub","","",
> + /*N0-N7*/ "","","","","bmc-ready","","","",
> + /*O0-O7*/ "","","","","","","fan0-bmc-cpld-enable","fan1-bmc-cpld-enable",
> + /*P0-P7*/ "fan2-bmc-cpld-enable","fan3-bmc-cpld-enable",
> + "reset-cause-pcie-slot1","reset-cause-pcie-slot2",
> + "reset-cause-pcie-slot3","reset-cause-pcie-slot4","","",
> + /*Q0-Q7*/ "","","","","","","","",
> + /*R0-R7*/ "","","","","","","","",
> + /*S0-S7*/ "","","power-p5v-usb","presence-bmc-tpm","","","","",
> + /*T0-T7*/ "","","","","","","","",
> + /*U0-U7*/ "","","","","","","","GND",
> + /*V0-V7*/ "bmc-slot1-ac-button","bmc-slot2-ac-button",
> + "bmc-slot3-ac-button","bmc-slot4-ac-button",
> + "","","","",
> + /*W0-W7*/ "","","","","","","","",
> + /*X0-X7*/ "","","","","","","","",
> + /*Y0-Y7*/ "","","","reset-cause-emmc","","","","",
> + /*Z0-Z7*/ "","","","","","","","";
> +};
> +
> +&gpio1 {
> + status = "okay";
Same question...
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH v1 1/2] ARM: dts: aspeed: greatlakes: Add gpio names
2023-03-29 8:36 ` Krzysztof Kozlowski
@ 2023-04-10 7:11 ` Delphine_CC_Chiu/WYHQ/Wiwynn
2023-04-10 15:21 ` Krzysztof Kozlowski
0 siblings, 1 reply; 7+ messages in thread
From: Delphine_CC_Chiu/WYHQ/Wiwynn @ 2023-04-10 7:11 UTC (permalink / raw)
To: Krzysztof Kozlowski, Delphine_CC_Chiu/WYHQ/Wiwynn,
patrick@stwcx.xyz, Rob Herring, Krzysztof Kozlowski, Joel Stanley,
Andrew Jeffery
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org
Thank you for reviewing.
> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Wednesday, March 29, 2023 4:37 PM
> To: Delphine_CC_Chiu/WYHQ/Wiwynn <Delphine_CC_Chiu@wiwynn.com>;
> patrick@stwcx.xyz; Rob Herring <robh+dt@kernel.org>; Krzysztof Kozlowski
> <krzysztof.kozlowski+dt@linaro.org>; Joel Stanley <joel@jms.id.au>; Andrew
> Jeffery <andrew@aj.id.au>
> Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-aspeed@lists.ozlabs.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v1 1/2] ARM: dts: aspeed: greatlakes: Add gpio names
>
> Security Reminder: Please be aware that this email is sent by an external
> sender.
>
> On 29/03/2023 10:32, Delphine CC Chiu wrote:
> > From: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
> >
> > Add GPIO names for SOC lines.
> >
> > Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
> > ---
> > .../dts/aspeed-bmc-facebook-greatlakes.dts | 49
> +++++++++++++++++++
> > 1 file changed, 49 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
> > b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
> > index 8c05bd56ce1e..59819115c39d 100644
> > --- a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
> > +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
> > @@ -238,4 +238,53 @@
> > &gpio0 {
> > pinctrl-names = "default";
> > pinctrl-0 = <&pinctrl_gpiu1_default &pinctrl_gpiu7_default>;
> > + status = "okay";
>
> Was it disabled before?
>
Yes, we have to enable gpio status for meeting aspeed-g6 device tree setting, and set net names for pulling gpio pin from application layer.
> > + gpio-line-names =
> > + /*A0-A7*/ "","","","","","","","",
> > + /*B0-B7*/ "power-bmc-nic","presence-ocp-debug",
> > + "power-bmc-slot1","power-bmc-slot2",
> > + "power-bmc-slot3","power-bmc-slot4","","",
> > + /*C0-C7*/ "presence-ocp-nic","","","reset-cause-nic-primary",
> > + "reset-cause-nic-secondary","","","",
> > + /*D0-D7*/ "","","","","","","","",
> > + /*E0-E7*/ "","","","","","","","",
> > + /*F0-F7*/ "slot1-bmc-reset-button","slot2-bmc-reset-button",
> > + "slot3-bmc-reset-button","slot4-bmc-reset-button",
> > + "","","","presence-emmc",
> > + /*G0-G7*/ "","","","","","","","",
> > + /*H0-H7*/ "","","","",
> > + "presence-mb-slot1","presence-mb-slot2",
> > + "presence-mb-slot3","presence-mb-slot4",
> > + /*I0-I7*/ "","","","","","","bb-bmc-button","",
> > + /*J0-J7*/ "","","","","","","","",
> > + /*K0-K7*/ "","","","","","","","",
> > + /*L0-L7*/ "","","","","","","","",
> > + /*M0-M7*/
> "","power-nic-bmc-enable","","usb-bmc-enable","","reset-cause-usb-hub","","",
> > + /*N0-N7*/ "","","","","bmc-ready","","","",
> > + /*O0-O7*/
> "","","","","","","fan0-bmc-cpld-enable","fan1-bmc-cpld-enable",
> > + /*P0-P7*/ "fan2-bmc-cpld-enable","fan3-bmc-cpld-enable",
> > + "reset-cause-pcie-slot1","reset-cause-pcie-slot2",
> > + "reset-cause-pcie-slot3","reset-cause-pcie-slot4","","",
> > + /*Q0-Q7*/ "","","","","","","","",
> > + /*R0-R7*/ "","","","","","","","",
> > + /*S0-S7*/ "","","power-p5v-usb","presence-bmc-tpm","","","","",
> > + /*T0-T7*/ "","","","","","","","",
> > + /*U0-U7*/ "","","","","","","","GND",
> > + /*V0-V7*/ "bmc-slot1-ac-button","bmc-slot2-ac-button",
> > + "bmc-slot3-ac-button","bmc-slot4-ac-button",
> > + "","","","",
> > + /*W0-W7*/ "","","","","","","","",
> > + /*X0-X7*/ "","","","","","","","",
> > + /*Y0-Y7*/ "","","","reset-cause-emmc","","","","",
> > + /*Z0-Z7*/ "","","","","","","",""; };
> > +
> > +&gpio1 {
> > + status = "okay";
>
> Same question...
Yes, the answer is same as above.
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v1 1/2] ARM: dts: aspeed: greatlakes: Add gpio names
2023-04-10 7:11 ` Delphine_CC_Chiu/WYHQ/Wiwynn
@ 2023-04-10 15:21 ` Krzysztof Kozlowski
2023-04-24 9:50 ` Delphine_CC_Chiu/WYHQ/Wiwynn
0 siblings, 1 reply; 7+ messages in thread
From: Krzysztof Kozlowski @ 2023-04-10 15:21 UTC (permalink / raw)
To: Delphine_CC_Chiu/WYHQ/Wiwynn, patrick@stwcx.xyz, Rob Herring,
Krzysztof Kozlowski, Joel Stanley, Andrew Jeffery
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org
On 10/04/2023 09:11, Delphine_CC_Chiu/WYHQ/Wiwynn wrote:
> Thank you for reviewing.
>
>> -----Original Message-----
>> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> Sent: Wednesday, March 29, 2023 4:37 PM
>> To: Delphine_CC_Chiu/WYHQ/Wiwynn <Delphine_CC_Chiu@wiwynn.com>;
>> patrick@stwcx.xyz; Rob Herring <robh+dt@kernel.org>; Krzysztof Kozlowski
>> <krzysztof.kozlowski+dt@linaro.org>; Joel Stanley <joel@jms.id.au>; Andrew
>> Jeffery <andrew@aj.id.au>
>> Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
>> linux-aspeed@lists.ozlabs.org; linux-kernel@vger.kernel.org
>> Subject: Re: [PATCH v1 1/2] ARM: dts: aspeed: greatlakes: Add gpio names
>>
>> Security Reminder: Please be aware that this email is sent by an external
>> sender.
>>
>> On 29/03/2023 10:32, Delphine CC Chiu wrote:
>>> From: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
>>>
>>> Add GPIO names for SOC lines.
>>>
>>> Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
>>> ---
>>> .../dts/aspeed-bmc-facebook-greatlakes.dts | 49
>> +++++++++++++++++++
>>> 1 file changed, 49 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
>>> b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
>>> index 8c05bd56ce1e..59819115c39d 100644
>>> --- a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
>>> +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
>>> @@ -238,4 +238,53 @@
>>> &gpio0 {
>>> pinctrl-names = "default";
>>> pinctrl-0 = <&pinctrl_gpiu1_default &pinctrl_gpiu7_default>;
>>> + status = "okay";
>>
>> Was it disabled before?
>>
> Yes,
Really? Can you provide any proof for this?
> we have to enable gpio status for meeting aspeed-g6 device tree setting, and set net names for pulling gpio pin from application layer.
What is "enable gpio status"? What does it mean to "meet aspeeg-g6
devicetree setting"?
What names have anything to do with my question?
Sorry, I cannot parse it at all.
>>> + gpio-line-names =
>>> + /*A0-A7*/ "","","","","","","","",
>>> + /*B0-B7*/ "power-bmc-nic","presence-ocp-debug",
>>> + "power-bmc-slot1","power-bmc-slot2",
>>> + "power-bmc-slot3","power-bmc-slot4","","",
>>> + /*C0-C7*/ "presence-ocp-nic","","","reset-cause-nic-primary",
>>> + "reset-cause-nic-secondary","","","",
>>> + /*D0-D7*/ "","","","","","","","",
>>> + /*E0-E7*/ "","","","","","","","",
>>> + /*F0-F7*/ "slot1-bmc-reset-button","slot2-bmc-reset-button",
>>> + "slot3-bmc-reset-button","slot4-bmc-reset-button",
>>> + "","","","presence-emmc",
>>> + /*G0-G7*/ "","","","","","","","",
>>> + /*H0-H7*/ "","","","",
>>> + "presence-mb-slot1","presence-mb-slot2",
>>> + "presence-mb-slot3","presence-mb-slot4",
>>> + /*I0-I7*/ "","","","","","","bb-bmc-button","",
>>> + /*J0-J7*/ "","","","","","","","",
>>> + /*K0-K7*/ "","","","","","","","",
>>> + /*L0-L7*/ "","","","","","","","",
>>> + /*M0-M7*/
>> "","power-nic-bmc-enable","","usb-bmc-enable","","reset-cause-usb-hub","","",
>>> + /*N0-N7*/ "","","","","bmc-ready","","","",
>>> + /*O0-O7*/
>> "","","","","","","fan0-bmc-cpld-enable","fan1-bmc-cpld-enable",
>>> + /*P0-P7*/ "fan2-bmc-cpld-enable","fan3-bmc-cpld-enable",
>>> + "reset-cause-pcie-slot1","reset-cause-pcie-slot2",
>>> + "reset-cause-pcie-slot3","reset-cause-pcie-slot4","","",
>>> + /*Q0-Q7*/ "","","","","","","","",
>>> + /*R0-R7*/ "","","","","","","","",
>>> + /*S0-S7*/ "","","power-p5v-usb","presence-bmc-tpm","","","","",
>>> + /*T0-T7*/ "","","","","","","","",
>>> + /*U0-U7*/ "","","","","","","","GND",
>>> + /*V0-V7*/ "bmc-slot1-ac-button","bmc-slot2-ac-button",
>>> + "bmc-slot3-ac-button","bmc-slot4-ac-button",
>>> + "","","","",
>>> + /*W0-W7*/ "","","","","","","","",
>>> + /*X0-X7*/ "","","","","","","","",
>>> + /*Y0-Y7*/ "","","","reset-cause-emmc","","","","",
>>> + /*Z0-Z7*/ "","","","","","","",""; };
>>> +
>>> +&gpio1 {
>>> + status = "okay";
>>
>> Same question...
> Yes, the answer is same as above.
So the same incorrect?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH v1 1/2] ARM: dts: aspeed: greatlakes: Add gpio names
2023-04-10 15:21 ` Krzysztof Kozlowski
@ 2023-04-24 9:50 ` Delphine_CC_Chiu/WYHQ/Wiwynn
0 siblings, 0 replies; 7+ messages in thread
From: Delphine_CC_Chiu/WYHQ/Wiwynn @ 2023-04-24 9:50 UTC (permalink / raw)
To: Krzysztof Kozlowski, Delphine_CC_Chiu/WYHQ/Wiwynn,
patrick@stwcx.xyz, Rob Herring, Krzysztof Kozlowski, Joel Stanley,
Andrew Jeffery
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org
> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Monday, April 10, 2023 11:21 PM
> To: Delphine_CC_Chiu/WYHQ/Wiwynn <Delphine_CC_Chiu@wiwynn.com>;
> patrick@stwcx.xyz; Rob Herring <robh+dt@kernel.org>; Krzysztof Kozlowski
> <krzysztof.kozlowski+dt@linaro.org>; Joel Stanley <joel@jms.id.au>; Andrew
> Jeffery <andrew@aj.id.au>
> Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-aspeed@lists.ozlabs.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v1 1/2] ARM: dts: aspeed: greatlakes: Add gpio names
>
> Security Reminder: Please be aware that this email is sent by an external
> sender.
>
> On 10/04/2023 09:11, Delphine_CC_Chiu/WYHQ/Wiwynn wrote:
> > Thank you for reviewing.
> >
> >> -----Original Message-----
> >> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> >> Sent: Wednesday, March 29, 2023 4:37 PM
> >> To: Delphine_CC_Chiu/WYHQ/Wiwynn
> <Delphine_CC_Chiu@wiwynn.com>;
> >> patrick@stwcx.xyz; Rob Herring <robh+dt@kernel.org>; Krzysztof
> >> Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Joel Stanley
> >> <joel@jms.id.au>; Andrew Jeffery <andrew@aj.id.au>
> >> Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> >> linux-aspeed@lists.ozlabs.org; linux-kernel@vger.kernel.org
> >> Subject: Re: [PATCH v1 1/2] ARM: dts: aspeed: greatlakes: Add gpio
> >> names
> >>
> >> Security Reminder: Please be aware that this email is sent by an
> >> external sender.
> >>
> >> On 29/03/2023 10:32, Delphine CC Chiu wrote:
> >>> From: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
> >>>
> >>> Add GPIO names for SOC lines.
> >>>
> >>> Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
> >>> ---
> >>> .../dts/aspeed-bmc-facebook-greatlakes.dts | 49
> >> +++++++++++++++++++
> >>> 1 file changed, 49 insertions(+)
> >>>
> >>> diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
> >>> b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
> >>> index 8c05bd56ce1e..59819115c39d 100644
> >>> --- a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
> >>> +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
> >>> @@ -238,4 +238,53 @@
> >>> &gpio0 {
> >>> pinctrl-names = "default";
> >>> pinctrl-0 = <&pinctrl_gpiu1_default &pinctrl_gpiu7_default>;
> >>> + status = "okay";
> >>
> >> Was it disabled before?
> >>
> > Yes,
>
> Really? Can you provide any proof for this?
Correct the answer after verifying - when gpio0 status property is not defined, it leads to device default enabled.
>
> > we have to enable gpio status for meeting aspeed-g6 device tree setting,
> and set net names for pulling gpio pin from application layer.
>
> What is "enable gpio status"? What does it mean to "meet aspeeg-g6
> devicetree setting"?
> What names have anything to do with my question?
>
> Sorry, I cannot parse it at all.
To describe more precisely, I surveyed the identification of of_device_is_available() in drivers/of/base.c.
It returns true if the status property is absent or set to "okay" or "ok", and false otherwise.
Because gpio0 status property hasn’t defined in aspeed-g6.dtsi, I set to "okay" to prevent that if it was disabled from other assignment.
>
> >>> + gpio-line-names =
> >>> + /*A0-A7*/ "","","","","","","","",
> >>> + /*B0-B7*/ "power-bmc-nic","presence-ocp-debug",
> >>> + "power-bmc-slot1","power-bmc-slot2",
> >>> + "power-bmc-slot3","power-bmc-slot4","","",
> >>> + /*C0-C7*/ "presence-ocp-nic","","","reset-cause-nic-primary",
> >>> + "reset-cause-nic-secondary","","","",
> >>> + /*D0-D7*/ "","","","","","","","",
> >>> + /*E0-E7*/ "","","","","","","","",
> >>> + /*F0-F7*/ "slot1-bmc-reset-button","slot2-bmc-reset-button",
> >>> + "slot3-bmc-reset-button","slot4-bmc-reset-button",
> >>> + "","","","presence-emmc",
> >>> + /*G0-G7*/ "","","","","","","","",
> >>> + /*H0-H7*/ "","","","",
> >>> + "presence-mb-slot1","presence-mb-slot2",
> >>> + "presence-mb-slot3","presence-mb-slot4",
> >>> + /*I0-I7*/ "","","","","","","bb-bmc-button","",
> >>> + /*J0-J7*/ "","","","","","","","",
> >>> + /*K0-K7*/ "","","","","","","","",
> >>> + /*L0-L7*/ "","","","","","","","",
> >>> + /*M0-M7*/
> >> "","power-nic-bmc-enable","","usb-bmc-enable","","reset-cause-usb-hub
> >> ","","",
> >>> + /*N0-N7*/ "","","","","bmc-ready","","","",
> >>> + /*O0-O7*/
> >> "","","","","","","fan0-bmc-cpld-enable","fan1-bmc-cpld-enable",
> >>> + /*P0-P7*/ "fan2-bmc-cpld-enable","fan3-bmc-cpld-enable",
> >>> + "reset-cause-pcie-slot1","reset-cause-pcie-slot2",
> >>> +
> "reset-cause-pcie-slot3","reset-cause-pcie-slot4","","",
> >>> + /*Q0-Q7*/ "","","","","","","","",
> >>> + /*R0-R7*/ "","","","","","","","",
> >>> + /*S0-S7*/ "","","power-p5v-usb","presence-bmc-tpm","","","","",
> >>> + /*T0-T7*/ "","","","","","","","",
> >>> + /*U0-U7*/ "","","","","","","","GND",
> >>> + /*V0-V7*/ "bmc-slot1-ac-button","bmc-slot2-ac-button",
> >>> + "bmc-slot3-ac-button","bmc-slot4-ac-button",
> >>> + "","","","",
> >>> + /*W0-W7*/ "","","","","","","","",
> >>> + /*X0-X7*/ "","","","","","","","",
> >>> + /*Y0-Y7*/ "","","","reset-cause-emmc","","","","",
> >>> + /*Z0-Z7*/ "","","","","","","",""; };
> >>> +
> >>> +&gpio1 {
> >>> + status = "okay";
> >>
> >> Same question...
> > Yes, the answer is same as above.
>
> So the same incorrect?
The status property of gpio1 was also default enabled.
For same reason as gpio0, I set to "okay" from this patch.
>
>
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2023-04-24 9:50 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-03-29 8:32 [PATCH v1 0/2] dts: aspeed: greatlakes: Update Greatlakes devicetree Delphine CC Chiu
2023-03-29 8:32 ` [PATCH v1 1/2] ARM: dts: aspeed: greatlakes: Add gpio names Delphine CC Chiu
2023-03-29 8:36 ` Krzysztof Kozlowski
2023-04-10 7:11 ` Delphine_CC_Chiu/WYHQ/Wiwynn
2023-04-10 15:21 ` Krzysztof Kozlowski
2023-04-24 9:50 ` Delphine_CC_Chiu/WYHQ/Wiwynn
2023-03-29 8:32 ` [PATCH v1 2/2] ARM: dts: aspeed: greatlakes: add mctp device Delphine CC Chiu
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