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[188.141.3.146]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45a1b789d68sm1106075e9.1.2025.08.13.14.18.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 13 Aug 2025 14:18:44 -0700 (PDT) Message-ID: Date: Wed, 13 Aug 2025 22:18:42 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 6/9] media: qcom: camss: Add support for CSID for sa8775p To: Vikram Sharma , rfoss@kernel.org, todor.too@gmail.com, mchehab@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org, hverkuil-cisco@xs4all.nl, cros-qcom-dts-watchers@chromium.org, catalin.marinas@arm.com, will@kernel.org Cc: linux-arm-kernel@lists.infradead.org, quic_svankada@quicinc.com, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250807121105.710072-1-quic_vikramsa@quicinc.com> <20250807121105.710072-7-quic_vikramsa@quicinc.com> From: Bryan O'Donoghue Content-Language: en-US In-Reply-To: <20250807121105.710072-7-quic_vikramsa@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 07/08/2025 13:11, Vikram Sharma wrote: > The CSID in sa8775p is version 690, This csid is different from > csid 780 w.r.t few bit-fields. > > Signed-off-by: Suresh Vankadara > Signed-off-by: Vikram Sharma > --- > .../platform/qcom/camss/camss-csid-gen3.c | 27 +++- > drivers/media/platform/qcom/camss/camss.c | 133 ++++++++++++++++++ > 2 files changed, 153 insertions(+), 7 deletions(-) > > diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen3.c b/drivers/media/platform/qcom/camss/camss-csid-gen3.c > index 433908a54baa..fc6a9787febe 100644 > --- a/drivers/media/platform/qcom/camss/camss-csid-gen3.c > +++ b/drivers/media/platform/qcom/camss/camss-csid-gen3.c > @@ -45,8 +45,11 @@ > #define CSID_CSI2_RX_IRQ_CLEAR 0xA4 > #define CSID_CSI2_RX_IRQ_SET 0xA8 > > +#define IS_CSID_690(csid) (csid->camss->res->version == CAMSS_8775P) > #define CSID_BUF_DONE_IRQ_STATUS 0x8C > -#define BUF_DONE_IRQ_STATUS_RDI_OFFSET (csid_is_lite(csid) ? 1 : 14) > +#define BUF_DONE_IRQ_STATUS_RDI_OFFSET (csid_is_lite(csid) ?\ > + 1 : (IS_CSID_690(csid) ?\ > + 13 : 14)) > #define CSID_BUF_DONE_IRQ_MASK 0x90 > #define CSID_BUF_DONE_IRQ_CLEAR 0x94 > #define CSID_BUF_DONE_IRQ_SET 0x98 > @@ -59,6 +62,7 @@ > > #define CSID_CSI2_RX_CFG0 0x200 > #define CSI2_RX_CFG0_NUM_ACTIVE_LANES 0 > +#define CSI2_RX_CFG0_VC_MODE 3 > #define CSI2_RX_CFG0_DL0_INPUT_SEL 4 > #define CSI2_RX_CFG0_PHY_NUM_SEL 20 > > @@ -66,7 +70,9 @@ > #define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0) > #define CSI2_RX_CFG1_VC_MODE BIT(2) > > -#define CSID_RDI_CFG0(rdi) (0x500 + 0x100 * (rdi)) > +#define CSID_RDI_CFG0(rdi) (csid_is_lite(csid) && IS_CSID_690(csid) ?\ > + (0x300 + 0x100 * (rdi)) :\ > + (0x500 + 0x100 * (rdi))) > #define RDI_CFG0_TIMESTAMP_EN BIT(6) > #define RDI_CFG0_TIMESTAMP_STB_SEL BIT(8) > #define RDI_CFG0_DECODE_FORMAT 12 > @@ -75,10 +81,14 @@ > #define RDI_CFG0_DT_ID 27 > #define RDI_CFG0_EN BIT(31) > > -#define CSID_RDI_CTRL(rdi) (0x504 + 0x100 * (rdi)) > +#define CSID_RDI_CTRL(rdi) (csid_is_lite(csid) && IS_CSID_690(csid) ?\ > + (0x304 + 0x100 * (rdi)) :\ > + (0x504 + 0x100 * (rdi))) > #define RDI_CTRL_START_CMD BIT(0) > > -#define CSID_RDI_CFG1(rdi) (0x510 + 0x100 * (rdi)) > +#define CSID_RDI_CFG1(rdi) (csid_is_lite(csid) && IS_CSID_690(csid) ?\ > + (0x310 + 0x100 * (rdi)) :\ > + (0x510 + 0x100 * (rdi))) > #define RDI_CFG1_DROP_H_EN BIT(5) > #define RDI_CFG1_DROP_V_EN BIT(6) > #define RDI_CFG1_CROP_H_EN BIT(7) > @@ -86,9 +96,12 @@ > #define RDI_CFG1_PIX_STORE BIT(10) > #define RDI_CFG1_PACKING_FORMAT_MIPI BIT(15) > > -#define CSID_RDI_IRQ_SUBSAMPLE_PATTERN(rdi) (0x548 + 0x100 * (rdi)) > -#define CSID_RDI_IRQ_SUBSAMPLE_PERIOD(rdi) (0x54C + 0x100 * (rdi)) > - > +#define CSID_RDI_IRQ_SUBSAMPLE_PATTERN(rdi) (csid_is_lite(csid) && IS_CSID_690(csid) ?\ > + (0x348 + 0x100 * (rdi)) :\ > + (0x548 + 0x100 * (rdi))) > +#define CSID_RDI_IRQ_SUBSAMPLE_PERIOD(rdi) (csid_is_lite(csid) && IS_CSID_690(csid) ?\ > + (0x34C + 0x100 * (rdi)) :\ > + (0x54C + 0x100 * (rdi))) > #define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1 > > static void __csid_configure_rx(struct csid_device *csid, > diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c > index 4767d4e7c306..5f1e267045cb 100644 > --- a/drivers/media/platform/qcom/camss/camss.c > +++ b/drivers/media/platform/qcom/camss/camss.c > @@ -2554,6 +2554,139 @@ static const struct camss_subdev_resources csiphy_res_8775p[] = { > }, > }; > > +static const struct camss_subdev_resources csid_res_8775p[] = { > + /* CSID0 */ > + { > + .regulators = {}, > + .clock = { "csid", "csiphy_rx"}, > + .clock_rate = { > + { 400000000, 400000000}, > + { 400000000, 400000000} > + }, > + .reg = { "csid0" }, > + .interrupt = { "csid0" }, > + .csid = { > + .is_lite = false, > + .hw_ops = &csid_ops_gen3, > + .parent_dev_ops = &vfe_parent_dev_ops, > + .formats = &csid_formats_gen2 > + } > + }, > + /* CSID1 */ > + { > + .regulators = {}, > + .clock = { "csid", "csiphy_rx"}, > + .clock_rate = { > + { 400000000, 400000000}, > + { 400000000, 400000000} > + }, > + .reg = { "csid1" }, > + .interrupt = { "csid1" }, > + .csid = { > + .is_lite = false, > + .hw_ops = &csid_ops_gen3, > + .parent_dev_ops = &vfe_parent_dev_ops, > + .formats = &csid_formats_gen2 > + } > + }, > + > + /* CSID2 (lite) */ > + { > + .regulators = {}, > + .clock = { "cpas_vfe_lite", "vfe_lite_ahb", > + "vfe_lite_csid", "vfe_lite_cphy_rx", > + "vfe_lite"}, > + .clock_rate = { > + { 0, 0, 400000000, 400000000, 0}, > + { 0, 0, 400000000, 480000000, 0} > + }, > + .reg = { "csid_lite0" }, > + .interrupt = { "csid_lite0" }, > + .csid = { > + .is_lite = true, > + .hw_ops = &csid_ops_gen3, > + .parent_dev_ops = &vfe_parent_dev_ops, > + .formats = &csid_formats_gen2 > + } > + }, > + /* CSID3 (lite) */ > + { > + .regulators = {}, > + .clock = { "cpas_vfe_lite", "vfe_lite_ahb", > + "vfe_lite_csid", "vfe_lite_cphy_rx", > + "vfe_lite"}, > + .clock_rate = { > + { 0, 0, 400000000, 400000000, 0}, > + { 0, 0, 400000000, 480000000, 0} > + }, > + .reg = { "csid_lite1" }, > + .interrupt = { "csid_lite1" }, > + .csid = { > + .is_lite = true, > + .hw_ops = &csid_ops_gen3, > + .parent_dev_ops = &vfe_parent_dev_ops, > + .formats = &csid_formats_gen2 > + } > + }, > + /* CSID4 (lite) */ > + { > + .regulators = {}, > + .clock = { "cpas_vfe_lite", "vfe_lite_ahb", > + "vfe_lite_csid", "vfe_lite_cphy_rx", > + "vfe_lite"}, > + .clock_rate = { > + { 0, 0, 400000000, 400000000, 0}, > + { 0, 0, 400000000, 480000000, 0} > + }, > + .reg = { "csid_lite2" }, > + .interrupt = { "csid_lite2" }, > + .csid = { > + .is_lite = true, > + .hw_ops = &csid_ops_gen3, > + .parent_dev_ops = &vfe_parent_dev_ops, > + .formats = &csid_formats_gen2 > + } > + }, > + /* CSID5 (lite) */ > + { > + .regulators = {}, > + .clock = { "cpas_vfe_lite", "vfe_lite_ahb", > + "vfe_lite_csid", "vfe_lite_cphy_rx", > + "vfe_lite"}, > + .clock_rate = { > + { 0, 0, 400000000, 400000000, 0}, > + { 0, 0, 400000000, 480000000, 0} > + }, > + .reg = { "csid_lite3" }, > + .interrupt = { "csid_lite3" }, > + .csid = { > + .is_lite = true, > + .hw_ops = &csid_ops_gen3, > + .parent_dev_ops = &vfe_parent_dev_ops, > + .formats = &csid_formats_gen2 > + } > + }, > + /* CSID6 (lite) */ > + { > + .regulators = {}, > + .clock = { "cpas_vfe_lite", "vfe_lite_ahb", > + "vfe_lite_csid", "vfe_lite_cphy_rx", > + "vfe_lite"}, > + .clock_rate = { > + { 0, 0, 400000000, 400000000, 0}, > + { 0, 0, 400000000, 480000000, 0} > + }, > + .reg = { "csid_lite4" }, > + .interrupt = { "csid_lite4" }, > + .csid = { > + .is_lite = true, > + .hw_ops = &csid_ops_gen3, > + .parent_dev_ops = &vfe_parent_dev_ops, > + .formats = &csid_formats_gen2 > + } > + }, > +}; > + > static const struct resources_icc icc_res_sa8775p[] = { > { > .name = "ahb", Reviewed-by: Bryan O'Donoghue