From: Ahmad Fatoum <a.fatoum@pengutronix.de>
To: Lothar Rubusch <l.rubusch@gmail.com>,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Pengutronix Kernel Team <kernel@pengutronix.de>
Subject: Re: [PATCHv2 13/23] ARM: dts: socfpga: add Enclustra boot-mode dtsi
Date: Wed, 23 Oct 2024 19:20:14 +0200 [thread overview]
Message-ID: <b6a6b9d8-ec2d-4360-9747-4b44d24e0b06@pengutronix.de> (raw)
In-Reply-To: <20241020194028.2272371-14-l.rubusch@gmail.com>
Hello Lothar,
On 20.10.24 21:40, Lothar Rubusch wrote:
> Add generic boot-mode support to Enclustra Arria10 and Cyclone5 boards.
> Some Enclustra carrier boards need hardware adjustments specific to the
> selected boot-mode.
Can you elaborate more on these hardware adjustments?
Do the different boot media e.g. share pins and can't be active at the same
time?
Thanks,
Ahmad
>
> Signed-off-by: Andreas Buerkler <andreas.buerkler@enclustra.com>
> Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
> ---
> .../socfpga_enclustra_mercury_bootmode_emmc.dtsi | 12 ++++++++++++
> .../socfpga_enclustra_mercury_bootmode_qspi.dtsi | 8 ++++++++
> .../socfpga_enclustra_mercury_bootmode_sdmmc.dtsi | 8 ++++++++
> 3 files changed, 28 insertions(+)
> create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_emmc.dtsi
> create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_qspi.dtsi
> create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_sdmmc.dtsi
>
> diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_emmc.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_emmc.dtsi
> new file mode 100644
> index 000000000..d79cb64da
> --- /dev/null
> +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_emmc.dtsi
> @@ -0,0 +1,12 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR MIT
> +/*
> + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
> + */
> +
> +&qspi {
> + status = "disabled";
> +};
> +
> +&mmc {
> + bus-width = <8>;
> +};
> diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_qspi.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_qspi.dtsi
> new file mode 100644
> index 000000000..5ba21dd8f
> --- /dev/null
> +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_qspi.dtsi
> @@ -0,0 +1,8 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR MIT
> +/*
> + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
> + */
> +
> +&mmc {
> + status = "disabled";
> +};
> diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_sdmmc.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_sdmmc.dtsi
> new file mode 100644
> index 000000000..2b102e0b6
> --- /dev/null
> +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_sdmmc.dtsi
> @@ -0,0 +1,8 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR MIT
> +/*
> + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
> + */
> +
> +&qspi {
> + status = "disabled";
> +};
--
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31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
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next prev parent reply other threads:[~2024-10-23 17:20 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-20 19:40 [PATCHv2 00/23] Add Enclustra Arria10 and Cyclone5 SoMs Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 01/23] ARM: dts: socfpga: fix typo Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 02/23] ARM: dts: socfpga: align bus name with bindings Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 03/23] ARM: dts: socfpga: align dma name with binding Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 04/23] ARM: dts: socfpga: align fpga-region name Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 05/23] ARM: dts: socfpga: add label to clock manager Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 06/23] ARM: dts: socfpga: add missing cells properties Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 07/23] ARM: dts: socfpga: fix missing ranges Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 08/23] ARM: dts: socfpga: add clock-frequency property Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 09/23] ARM: dts: socfpga: add ranges property to sram Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 10/23] ARM: dts: socfpga: remove arria10 reset-names Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 11/23] ARM: socfpga: dts: add compatibility for arria10 Lothar Rubusch
2024-10-21 7:05 ` Krzysztof Kozlowski
2024-10-20 19:40 ` [PATCHv2 12/23] ARM: socfpga: dts: add a10 clock binding yaml Lothar Rubusch
2024-10-20 22:21 ` Rob Herring (Arm)
2024-10-21 7:04 ` Krzysztof Kozlowski
2024-10-24 6:10 ` Lothar Rubusch
2024-10-24 6:24 ` Krzysztof Kozlowski
2024-10-25 6:59 ` Lothar Rubusch
2024-10-25 8:01 ` Krzysztof Kozlowski
2024-10-20 19:40 ` [PATCHv2 13/23] ARM: dts: socfpga: add Enclustra boot-mode dtsi Lothar Rubusch
2024-10-23 17:20 ` Ahmad Fatoum [this message]
2024-10-24 6:15 ` Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 14/23] ARM: dts: socfpga: add Enclustra base-board dtsi Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 15/23] ARM: dts: socfpga: add Enclustra Mercury SA1 Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 16/23] dt-bindings: altera: " Lothar Rubusch
2024-10-21 7:47 ` Krzysztof Kozlowski
2024-10-20 19:40 ` [PATCHv2 17/23] ARM: dts: socfpga: add Enclustra Mercury+ SA2 Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 18/23] dt-bindings: altera: add binding for " Lothar Rubusch
2024-10-21 7:47 ` Krzysztof Kozlowski
2024-10-20 19:40 ` [PATCHv2 19/23] ARM: dts: socfpga: add Mercury AA1 combinations Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 20/23] dt-bindings: altera: " Lothar Rubusch
2024-10-21 7:48 ` Krzysztof Kozlowski
2024-10-20 19:40 ` [PATCHv2 21/23] ARM: dts: socfpga: removal of generic PE1 dts Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 22/23] dt-bindings: altera: " Lothar Rubusch
2024-10-21 7:48 ` Krzysztof Kozlowski
2024-10-20 19:40 ` [PATCHv2 23/23] ARM: dts: socfpga: add Enclustra SoM dts files Lothar Rubusch
2024-10-21 17:58 ` [PATCHv2 00/23] Add Enclustra Arria10 and Cyclone5 SoMs Rob Herring (Arm)
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