* [PATCH v5 01/21] ARM: dts: aspeed: yosemite4: Revise i2c-mux devices
2024-01-31 8:41 [PATCH v5 00/21] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
@ 2024-01-31 8:41 ` Delphine CC Chiu
2024-02-01 3:46 ` Andrew Jeffery
2024-01-31 8:41 ` [PATCH v5 02/21] ARM: dts: aspeed: yosemite4: Enable adc15 Delphine CC Chiu
` (19 subsequent siblings)
20 siblings, 1 reply; 37+ messages in thread
From: Delphine CC Chiu @ 2024-01-31 8:41 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Revise Yosemite 4 devicetree for devices behind i2c-mux
- Add gpio and eeprom behind i2c-mux
- Remove redundant idle-state setting for i2c-mux
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 381 ++++++++++++++++--
1 file changed, 347 insertions(+), 34 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index 64075cc41d92..dac58d3ea63c 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -17,6 +17,25 @@ aliases {
serial6 = &uart7;
serial7 = &uart8;
serial8 = &uart9;
+
+ i2c16 = &imux16;
+ i2c17 = &imux17;
+ i2c18 = &imux18;
+ i2c19 = &imux19;
+ i2c20 = &imux20;
+ i2c21 = &imux21;
+ i2c22 = &imux22;
+ i2c23 = &imux23;
+ i2c24 = &imux24;
+ i2c25 = &imux25;
+ i2c26 = &imux26;
+ i2c27 = &imux27;
+ i2c28 = &imux28;
+ i2c29 = &imux29;
+ i2c30 = &imux30;
+ i2c31 = &imux31;
+ i2c32 = &imux32;
+ i2c33 = &imux33;
};
chosen {
@@ -259,9 +278,109 @@ &i2c8 {
bus-frequency = <400000>;
i2c-mux@70 {
compatible = "nxp,pca9544";
- idle-state = <0>;
i2c-mux-idle-disconnect;
reg = <0x70>;
+
+ imux16: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ gpio@49 {
+ compatible = "nxp,pca9537";
+ reg = <0x49>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c128";
+ reg = <0x51>;
+ };
+
+ eeprom@54 {
+ compatible = "atmel,24c128";
+ reg = <0x54>;
+ };
+ };
+
+ imux17: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ gpio@49 {
+ compatible = "nxp,pca9537";
+ reg = <0x49>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c128";
+ reg = <0x51>;
+ };
+
+ eeprom@54 {
+ compatible = "atmel,24c128";
+ reg = <0x54>;
+ };
+ };
+
+ imux18: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ gpio@49 {
+ compatible = "nxp,pca9537";
+ reg = <0x49>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c128";
+ reg = <0x51>;
+ };
+
+ eeprom@54 {
+ compatible = "atmel,24c128";
+ reg = <0x54>;
+ };
+ };
+
+ imux19: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ gpio@49 {
+ compatible = "nxp,pca9537";
+ reg = <0x49>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c128";
+ reg = <0x51>;
+ };
+
+ eeprom@54 {
+ compatible = "atmel,24c128";
+ reg = <0x54>;
+ };
+ };
};
};
@@ -270,15 +389,174 @@ &i2c9 {
bus-frequency = <400000>;
i2c-mux@71 {
compatible = "nxp,pca9544";
- idle-state = <0>;
i2c-mux-idle-disconnect;
reg = <0x71>;
+
+ imux20: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ gpio@49 {
+ compatible = "nxp,pca9537";
+ reg = <0x49>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c128";
+ reg = <0x51>;
+ };
+
+ eeprom@54 {
+ compatible = "atmel,24c128";
+ reg = <0x54>;
+ };
+ };
+
+ imux21: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ gpio@49 {
+ compatible = "nxp,pca9537";
+ reg = <0x49>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c128";
+ reg = <0x51>;
+ };
+
+ eeprom@54 {
+ compatible = "atmel,24c128";
+ reg = <0x54>;
+ };
+ };
+
+ imux22: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ gpio@49 {
+ compatible = "nxp,pca9537";
+ reg = <0x49>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c128";
+ reg = <0x51>;
+ };
+
+ eeprom@54 {
+ compatible = "atmel,24c128";
+ reg = <0x54>;
+ };
+ };
+
+ imux23: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+
+ gpio@49 {
+ compatible = "nxp,pca9537";
+ reg = <0x49>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c128";
+ reg = <0x51>;
+ };
+
+ eeprom@54 {
+ compatible = "atmel,24c128";
+ reg = <0x54>;
+ };
+ };
};
};
&i2c10 {
status = "okay";
bus-frequency = <400000>;
+ i2c-mux@74 {
+ compatible = "nxp,pca9544";
+ i2c-mux-idle-disconnect;
+ reg = <0x74>;
+
+ imux28: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ gpio@20 {
+ compatible = "nxp,pca9506";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@21 {
+ compatible = "nxp,pca9506";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9506";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@23 {
+ compatible = "nxp,pca9506";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@24 {
+ compatible = "nxp,pca9506";
+ reg = <0x24>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names =
+ "","","","",
+ "NIC0-MAIN-PWR-EN","NIC1-MAIN-PWR-EN",
+ "NIC2-MAIN-PWR-EN","NIC3-MAIN-PWR-EN",
+ "","","","","","","","",
+ "","","","","","","","",
+ "","","","","","","","";
+ };
+ };
+
+ imux29: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
};
&i2c11 {
@@ -433,16 +711,14 @@ eeprom@51 {
reg = <0x51>;
};
- i2c-mux@71 {
- compatible = "nxp,pca9846";
+ i2c-mux@74 {
+ compatible = "nxp,pca9546";
#address-cells = <1>;
#size-cells = <0>;
-
- idle-state = <0>;
i2c-mux-idle-disconnect;
- reg = <0x71>;
+ reg = <0x74>;
- i2c@0 {
+ imux30: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
@@ -450,26 +726,26 @@ i2c@0 {
adc@1f {
compatible = "ti,adc128d818";
reg = <0x1f>;
- ti,mode = /bits/ 8 <2>;
+ ti,mode = /bits/ 8 <1>;
};
pwm@20{
- compatible = "max31790";
+ compatible = "maxim,max31790";
+ pwm-as-tach = <4 5>;
reg = <0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
};
gpio@22{
compatible = "ti,tca6424";
reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
};
- pwm@23{
- compatible = "max31790";
- reg = <0x23>;
- #address-cells = <1>;
- #size-cells = <0>;
+ pwm@2f{
+ compatible = "maxim,max31790";
+ pwm-as-tach = <4 5>;
+ reg = <0x2f>;
};
adc@33 {
@@ -492,34 +768,34 @@ gpio@61 {
};
};
- i2c@1 {
+ imux31: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
- reg = <0>;
+ reg = <1>;
adc@1f {
compatible = "ti,adc128d818";
reg = <0x1f>;
- ti,mode = /bits/ 8 <2>;
+ ti,mode = /bits/ 8 <1>;
};
pwm@20{
- compatible = "max31790";
+ compatible = "maxim,max31790";
+ pwm-as-tach = <4 5>;
reg = <0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
};
gpio@22{
compatible = "ti,tca6424";
reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
};
- pwm@23{
- compatible = "max31790";
- reg = <0x23>;
- #address-cells = <1>;
- #size-cells = <0>;
+ pwm@2f{
+ compatible = "maxim,max31790";
+ pwm-as-tach = <4 5>;
+ reg = <0x2f>;
};
adc@33 {
@@ -547,12 +823,10 @@ i2c-mux@73 {
compatible = "nxp,pca9544";
#address-cells = <1>;
#size-cells = <0>;
-
- idle-state = <0>;
i2c-mux-idle-disconnect;
reg = <0x73>;
- i2c@0 {
+ imux32: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
@@ -563,10 +837,10 @@ adc@35 {
};
};
- i2c@1 {
+ imux33: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
- reg = <0>;
+ reg = <1>;
adc@35 {
compatible = "maxim,max11617";
@@ -589,9 +863,48 @@ mctp@10 {
i2c-mux@72 {
compatible = "nxp,pca9544";
- idle-state = <0>;
i2c-mux-idle-disconnect;
reg = <0x72>;
+
+ imux24: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ temperature-sensor@1f {
+ compatible = "ti,tmp421";
+ reg = <0x1f>;
+ };
+ };
+
+ imux25: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ temperature-sensor@1f {
+ compatible = "ti,tmp421";
+ reg = <0x1f>;
+ };
+ };
+
+ imux26: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ temperature-sensor@1f {
+ compatible = "ti,tmp421";
+ reg = <0x1f>;
+ };
+ };
+
+ imux27: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ temperature-sensor@1f {
+ compatible = "ti,tmp421";
+ reg = <0x1f>;
+ };
+ };
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v5 01/21] ARM: dts: aspeed: yosemite4: Revise i2c-mux devices
2024-01-31 8:41 ` [PATCH v5 01/21] ARM: dts: aspeed: yosemite4: Revise i2c-mux devices Delphine CC Chiu
@ 2024-02-01 3:46 ` Andrew Jeffery
0 siblings, 0 replies; 37+ messages in thread
From: Andrew Jeffery @ 2024-02-01 3:46 UTC (permalink / raw)
To: Delphine CC Chiu, patrick, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Joel Stanley
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel
Hi Delphine,
On Wed, 2024-01-31 at 16:41 +0800, Delphine CC Chiu wrote:
> Revise Yosemite 4 devicetree for devices behind i2c-mux
> - Add gpio and eeprom behind i2c-mux
> - Remove redundant idle-state setting for i2c-mux
Generally if you find yourself listing things the patch does in the
commit message it's an indicator you should split the patch up.
It looks like there's a lot of stuff to be fixed, but it doesn't need
to all be fixed in the one commit (as 01/21 suggests I guess). The
devicetree is already inaccurate, it's okay if a subset of the
inaccuracies survive for another patch or so.
Otherwise, if they must be changed together, it would be good to have a
description of *why*. Broadly, the commit message should explain *why*
the change is need regardless, not discuss *what* the patch changes
(that's evident from the patch itself).
>
> Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
> ---
> .../aspeed/aspeed-bmc-facebook-yosemite4.dts | 381 ++++++++++++++++--
> 1 file changed, 347 insertions(+), 34 deletions(-)
>
>
> - i2c-mux@71 {
> - compatible = "nxp,pca9846";
> + i2c-mux@74 {
> + compatible = "nxp,pca9546";
Aside from splitting the patch on adding more devices and removing the
redundant idle-state settings, things like this should probably be
separate too.
Why was the address changed? Was it always wrong? Or has there been a
new revision of the board? A separate commit with some explanation here
would be useful.
> #address-cells = <1>;
> #size-cells = <0>;
> -
> - idle-state = <0>;
> i2c-mux-idle-disconnect;
> - reg = <0x71>;
> + reg = <0x74>;
>
> - i2c@0 {
> + imux30: i2c@0 {
> #address-cells = <1>;
> #size-cells = <0>;
> reg = <0>;
> @@ -450,26 +726,26 @@ i2c@0 {
> adc@1f {
> compatible = "ti,adc128d818";
> reg = <0x1f>;
> - ti,mode = /bits/ 8 <2>;
> + ti,mode = /bits/ 8 <1>;
This isn't discussed anywhere. There should probably be a separate
change for anything adc128d818-related that explains what's going on
here.
> };
>
> pwm@20{
> - compatible = "max31790";
> + compatible = "maxim,max31790";
> + pwm-as-tach = <4 5>;
> reg = <0x20>;
> - #address-cells = <1>;
> - #size-cells = <0>;
This also isn't discussed anywhere. There should probably be a separate
change for anything max31790-related that explains what's going on
here.
> };
>
> gpio@22{
> compatible = "ti,tca6424";
> reg = <0x22>;
> + gpio-controller;
> + #gpio-cells = <2>;
Also not discussed. Separate change for anything tca6424-related that
explains what's going on here.
> };
>
> - pwm@23{
> - compatible = "max31790";
> - reg = <0x23>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> + pwm@2f{
> + compatible = "maxim,max31790";
> + pwm-as-tach = <4 5>;
> + reg = <0x2f>;
> };
Should go in the max31790-related patch.
>
> adc@33 {
> @@ -492,34 +768,34 @@ gpio@61 {
> };
> };
>
> - i2c@1 {
> + imux31: i2c@1 {
> #address-cells = <1>;
> #size-cells = <0>;
> - reg = <0>;
> + reg = <1>;
>
> adc@1f {
> compatible = "ti,adc128d818";
> reg = <0x1f>;
> - ti,mode = /bits/ 8 <2>;
> + ti,mode = /bits/ 8 <1>;
Should go in the adc128d818 patch
> };
>
> pwm@20{
> - compatible = "max31790";
> + compatible = "maxim,max31790";
> + pwm-as-tach = <4 5>;
> reg = <0x20>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> };
Should go in the max31790 patch
>
> gpio@22{
> compatible = "ti,tca6424";
> reg = <0x22>;
> + gpio-controller;
> + #gpio-cells = <2>;
Should go in the tca6424 patch
> };
>
> - pwm@23{
> - compatible = "max31790";
> - reg = <0x23>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> + pwm@2f{
> + compatible = "maxim,max31790";
> + pwm-as-tach = <4 5>;
> + reg = <0x2f>;
Should go in the max31790 patch
Andrew
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v5 02/21] ARM: dts: aspeed: yosemite4: Enable adc15
2024-01-31 8:41 [PATCH v5 00/21] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
2024-01-31 8:41 ` [PATCH v5 01/21] ARM: dts: aspeed: yosemite4: Revise i2c-mux devices Delphine CC Chiu
@ 2024-01-31 8:41 ` Delphine CC Chiu
2024-02-01 4:13 ` Andrew Jeffery
2024-01-31 8:41 ` [PATCH v5 03/21] ARM: dts: aspeed: yosemite4: Enable spi-gpio setting Delphine CC Chiu
` (18 subsequent siblings)
20 siblings, 1 reply; 37+ messages in thread
From: Delphine CC Chiu @ 2024-01-31 8:41 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Enable Yosemite 4 adc15 config
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index dac58d3ea63c..6846aab893ad 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -51,7 +51,7 @@ iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>,
<&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>,
- <&adc1 0>, <&adc1 1>;
+ <&adc1 0>, <&adc1 1>, <&adc1 7>;
};
};
@@ -920,10 +920,10 @@ &pinctrl_adc4_default &pinctrl_adc5_default
&adc1 {
ref_voltage = <2500>;
status = "okay";
- pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default>;
+ pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default
+ &pinctrl_adc15_default>;
};
-
&ehci0 {
status = "okay";
};
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v5 02/21] ARM: dts: aspeed: yosemite4: Enable adc15
2024-01-31 8:41 ` [PATCH v5 02/21] ARM: dts: aspeed: yosemite4: Enable adc15 Delphine CC Chiu
@ 2024-02-01 4:13 ` Andrew Jeffery
0 siblings, 0 replies; 37+ messages in thread
From: Andrew Jeffery @ 2024-02-01 4:13 UTC (permalink / raw)
To: Delphine CC Chiu, patrick, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Joel Stanley
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel
On Wed, 2024-01-31 at 16:41 +0800, Delphine CC Chiu wrote:
> Enable Yosemite 4 adc15 config
This should have a description. What's motivating the change? Why make
it? What are we monitoring with ADC15? Why wasn't it necessary
previously?
The expectations on commit messages are outlined here:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst?h=v6.7#n45
Andrew
>
> Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
> ---
> arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> index dac58d3ea63c..6846aab893ad 100644
> --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> @@ -51,7 +51,7 @@ iio-hwmon {
> compatible = "iio-hwmon";
> io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>,
> <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>,
> - <&adc1 0>, <&adc1 1>;
> + <&adc1 0>, <&adc1 1>, <&adc1 7>;
> };
> };
>
> @@ -920,10 +920,10 @@ &pinctrl_adc4_default &pinctrl_adc5_default
> &adc1 {
> ref_voltage = <2500>;
> status = "okay";
> - pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default>;
> + pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default
> + &pinctrl_adc15_default>;
> };
>
> -
> &ehci0 {
> status = "okay";
> };
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v5 03/21] ARM: dts: aspeed: yosemite4: Enable spi-gpio setting
2024-01-31 8:41 [PATCH v5 00/21] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
2024-01-31 8:41 ` [PATCH v5 01/21] ARM: dts: aspeed: yosemite4: Revise i2c-mux devices Delphine CC Chiu
2024-01-31 8:41 ` [PATCH v5 02/21] ARM: dts: aspeed: yosemite4: Enable adc15 Delphine CC Chiu
@ 2024-01-31 8:41 ` Delphine CC Chiu
2024-02-01 4:15 ` Andrew Jeffery
2024-01-31 8:41 ` [PATCH v5 04/21] ARM: dts: aspeed: yosemite4: Enable watchdog2 Delphine CC Chiu
` (17 subsequent siblings)
20 siblings, 1 reply; 37+ messages in thread
From: Delphine CC Chiu @ 2024-01-31 8:41 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
enable spi-gpio setting for spi flash
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index 6846aab893ad..ea8fd3ec0982 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -53,6 +53,24 @@ iio-hwmon {
<&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>,
<&adc1 0>, <&adc1 1>, <&adc1 7>;
};
+
+ spi_gpio: spi-gpio {
+ compatible = "spi-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-sck = <&gpio0 ASPEED_GPIO(X, 3) GPIO_ACTIVE_HIGH>;
+ gpio-mosi = <&gpio0 ASPEED_GPIO(X, 4) GPIO_ACTIVE_HIGH>;
+ gpio-miso = <&gpio0 ASPEED_GPIO(X, 5) GPIO_ACTIVE_HIGH>;
+ num-chipselects = <1>;
+ cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>;
+
+ tpmdev@0 {
+ compatible = "tcg,tpm_tis-spi";
+ spi-max-frequency = <33000000>;
+ reg = <0>;
+ };
+ };
};
&uart1 {
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v5 03/21] ARM: dts: aspeed: yosemite4: Enable spi-gpio setting
2024-01-31 8:41 ` [PATCH v5 03/21] ARM: dts: aspeed: yosemite4: Enable spi-gpio setting Delphine CC Chiu
@ 2024-02-01 4:15 ` Andrew Jeffery
0 siblings, 0 replies; 37+ messages in thread
From: Andrew Jeffery @ 2024-02-01 4:15 UTC (permalink / raw)
To: Delphine CC Chiu, patrick, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Joel Stanley
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel
On Wed, 2024-01-31 at 16:41 +0800, Delphine CC Chiu wrote:
> enable spi-gpio setting for spi flash
I suspect I know what's motivating this as a design, but can you add an
explanation to the commit message?
Again, expectations on commit messages are outlined here:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst?h=v6.7#n45
Andrew
>
> Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
> ---
> .../aspeed/aspeed-bmc-facebook-yosemite4.dts | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> index 6846aab893ad..ea8fd3ec0982 100644
> --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> @@ -53,6 +53,24 @@ iio-hwmon {
> <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>,
> <&adc1 0>, <&adc1 1>, <&adc1 7>;
> };
> +
> + spi_gpio: spi-gpio {
> + compatible = "spi-gpio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + gpio-sck = <&gpio0 ASPEED_GPIO(X, 3) GPIO_ACTIVE_HIGH>;
> + gpio-mosi = <&gpio0 ASPEED_GPIO(X, 4) GPIO_ACTIVE_HIGH>;
> + gpio-miso = <&gpio0 ASPEED_GPIO(X, 5) GPIO_ACTIVE_HIGH>;
> + num-chipselects = <1>;
> + cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>;
> +
> + tpmdev@0 {
> + compatible = "tcg,tpm_tis-spi";
> + spi-max-frequency = <33000000>;
> + reg = <0>;
> + };
> + };
> };
>
> &uart1 {
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v5 04/21] ARM: dts: aspeed: yosemite4: Enable watchdog2
2024-01-31 8:41 [PATCH v5 00/21] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
` (2 preceding siblings ...)
2024-01-31 8:41 ` [PATCH v5 03/21] ARM: dts: aspeed: yosemite4: Enable spi-gpio setting Delphine CC Chiu
@ 2024-01-31 8:41 ` Delphine CC Chiu
2024-02-01 5:34 ` Andrew Jeffery
2024-01-31 8:41 ` [PATCH v5 05/21] ARM: dts: aspeed: yosemite4: Revise quad mode to dual mode Delphine CC Chiu
` (16 subsequent siblings)
20 siblings, 1 reply; 37+ messages in thread
From: Delphine CC Chiu @ 2024-01-31 8:41 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
enable watchdog2 setting
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index ea8fd3ec0982..f8bfdefbefc6 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -120,6 +120,13 @@ &wdt1 {
aspeed,ext-pulse-duration = <256>;
};
+&wdt2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdtrst2_default>;
+ aspeed,reset-type = "system";
+};
+
&mac2 {
status = "okay";
pinctrl-names = "default";
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v5 04/21] ARM: dts: aspeed: yosemite4: Enable watchdog2
2024-01-31 8:41 ` [PATCH v5 04/21] ARM: dts: aspeed: yosemite4: Enable watchdog2 Delphine CC Chiu
@ 2024-02-01 5:34 ` Andrew Jeffery
0 siblings, 0 replies; 37+ messages in thread
From: Andrew Jeffery @ 2024-02-01 5:34 UTC (permalink / raw)
To: Delphine CC Chiu, patrick, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Joel Stanley
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel
On Wed, 2024-01-31 at 16:41 +0800, Delphine CC Chiu wrote:
> enable watchdog2 setting
Maybe "Enable watchdog2 for SoC reboot" at least?
Andrew
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v5 05/21] ARM: dts: aspeed: yosemite4: Revise quad mode to dual mode
2024-01-31 8:41 [PATCH v5 00/21] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
` (3 preceding siblings ...)
2024-01-31 8:41 ` [PATCH v5 04/21] ARM: dts: aspeed: yosemite4: Enable watchdog2 Delphine CC Chiu
@ 2024-01-31 8:41 ` Delphine CC Chiu
2024-02-01 4:22 ` Andrew Jeffery
2024-01-31 8:41 ` [PATCH v5 06/21] ARM: dts: aspeed: yosemite4: Revise power sensor adm1281 for schematic change Delphine CC Chiu
` (15 subsequent siblings)
20 siblings, 1 reply; 37+ messages in thread
From: Delphine CC Chiu @ 2024-01-31 8:41 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Revise quad mode to dual mode to avoid WP pin influnece the SPI
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index f8bfdefbefc6..23006dca5f26 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -149,15 +149,17 @@ flash@0 {
status = "okay";
m25p,fast-read;
label = "bmc";
- spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
spi-max-frequency = <50000000>;
-#include "openbmc-flash-layout-64.dtsi"
+#include "openbmc-flash-layout-128.dtsi"
};
flash@1 {
status = "okay";
m25p,fast-read;
label = "bmc2";
- spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
spi-max-frequency = <50000000>;
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v5 05/21] ARM: dts: aspeed: yosemite4: Revise quad mode to dual mode
2024-01-31 8:41 ` [PATCH v5 05/21] ARM: dts: aspeed: yosemite4: Revise quad mode to dual mode Delphine CC Chiu
@ 2024-02-01 4:22 ` Andrew Jeffery
0 siblings, 0 replies; 37+ messages in thread
From: Andrew Jeffery @ 2024-02-01 4:22 UTC (permalink / raw)
To: Delphine CC Chiu, patrick, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Joel Stanley
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel
On Wed, 2024-01-31 at 16:41 +0800, Delphine CC Chiu wrote:
> Revise quad mode to dual mode to avoid WP pin influnece the SPI
What do you mean by this? Can you unpack what's going on a little more
in the commit message?
Andrew
>
> Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
> ---
> .../arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> index f8bfdefbefc6..23006dca5f26 100644
> --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> @@ -149,15 +149,17 @@ flash@0 {
> status = "okay";
> m25p,fast-read;
> label = "bmc";
> - spi-rx-bus-width = <4>;
> + spi-tx-bus-width = <2>;
> + spi-rx-bus-width = <2>;
> spi-max-frequency = <50000000>;
> -#include "openbmc-flash-layout-64.dtsi"
> +#include "openbmc-flash-layout-128.dtsi"
> };
> flash@1 {
> status = "okay";
> m25p,fast-read;
> label = "bmc2";
> - spi-rx-bus-width = <4>;
> + spi-tx-bus-width = <2>;
> + spi-rx-bus-width = <2>;
> spi-max-frequency = <50000000>;
> };
> };
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v5 06/21] ARM: dts: aspeed: yosemite4: Revise power sensor adm1281 for schematic change
2024-01-31 8:41 [PATCH v5 00/21] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
` (4 preceding siblings ...)
2024-01-31 8:41 ` [PATCH v5 05/21] ARM: dts: aspeed: yosemite4: Revise quad mode to dual mode Delphine CC Chiu
@ 2024-01-31 8:41 ` Delphine CC Chiu
2024-02-01 4:24 ` Andrew Jeffery
2024-01-31 8:41 ` [PATCH v5 07/21] ARM: dts: aspeed: yosemite4: Add gpio pca9506 Delphine CC Chiu
` (14 subsequent siblings)
20 siblings, 1 reply; 37+ messages in thread
From: Delphine CC Chiu @ 2024-01-31 8:41 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Revise power sensor adm1281 for yosemite4 schematic change
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 24 ++++++++++++-------
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index 23006dca5f26..af9f7067c57c 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -176,8 +176,9 @@ mctp@10 {
};
power-sensor@40 {
- compatible = "adi,adm1278";
+ compatible = "adi,adm1281";
reg = <0x40>;
+ shunt-resistor-micro-ohms = <500>;
};
};
@@ -193,8 +194,9 @@ mctp@10 {
};
power-sensor@40 {
- compatible = "adi,adm1278";
+ compatible = "adi,adm1281";
reg = <0x40>;
+ shunt-resistor-micro-ohms = <500>;
};
};
@@ -210,8 +212,9 @@ mctp@10 {
};
power-sensor@40 {
- compatible = "adi,adm1278";
+ compatible = "adi,adm1281";
reg = <0x40>;
+ shunt-resistor-micro-ohms = <500>;
};
};
@@ -227,8 +230,9 @@ mctp@10 {
};
power-sensor@40 {
- compatible = "adi,adm1278";
+ compatible = "adi,adm1281";
reg = <0x40>;
+ shunt-resistor-micro-ohms = <500>;
};
};
@@ -244,8 +248,9 @@ mctp@10 {
};
power-sensor@40 {
- compatible = "adi,adm1278";
+ compatible = "adi,adm1281";
reg = <0x40>;
+ shunt-resistor-micro-ohms = <500>;
};
};
@@ -261,8 +266,9 @@ mctp@10 {
};
power-sensor@40 {
- compatible = "adi,adm1278";
+ compatible = "adi,adm1281";
reg = <0x40>;
+ shunt-resistor-micro-ohms = <500>;
};
};
@@ -278,8 +284,9 @@ mctp@10 {
};
power-sensor@40 {
- compatible = "adi,adm1278";
+ compatible = "adi,adm1281";
reg = <0x40>;
+ shunt-resistor-micro-ohms = <500>;
};
};
@@ -295,8 +302,9 @@ mctp@10 {
};
power-sensor@40 {
- compatible = "adi,adm1278";
+ compatible = "adi,adm1281";
reg = <0x40>;
+ shunt-resistor-micro-ohms = <500>;
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v5 06/21] ARM: dts: aspeed: yosemite4: Revise power sensor adm1281 for schematic change
2024-01-31 8:41 ` [PATCH v5 06/21] ARM: dts: aspeed: yosemite4: Revise power sensor adm1281 for schematic change Delphine CC Chiu
@ 2024-02-01 4:24 ` Andrew Jeffery
0 siblings, 0 replies; 37+ messages in thread
From: Andrew Jeffery @ 2024-02-01 4:24 UTC (permalink / raw)
To: Delphine CC Chiu, patrick, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Joel Stanley
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel
On Wed, 2024-01-31 at 16:41 +0800, Delphine CC Chiu wrote:
> Revise power sensor adm1281 for yosemite4 schematic change
>
> Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
I'm not enamoured by the lack of a description, but at least the
subject provides the motivation.
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v5 07/21] ARM: dts: aspeed: yosemite4: Add gpio pca9506
2024-01-31 8:41 [PATCH v5 00/21] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
` (5 preceding siblings ...)
2024-01-31 8:41 ` [PATCH v5 06/21] ARM: dts: aspeed: yosemite4: Revise power sensor adm1281 for schematic change Delphine CC Chiu
@ 2024-01-31 8:41 ` Delphine CC Chiu
2024-02-01 5:35 ` Andrew Jeffery
2024-01-31 8:41 ` [PATCH v5 08/21] ARM: dts: aspeed: yosemite4: Remove space for adm1272 compatible Delphine CC Chiu
` (13 subsequent siblings)
20 siblings, 1 reply; 37+ messages in thread
From: Delphine CC Chiu @ 2024-01-31 8:41 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Add gpio pca9506 I/O expander for yv4 use
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 251 ++++++++++++++++++
1 file changed, 251 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index af9f7067c57c..b1775b5a6782 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -175,6 +175,34 @@ mctp@10 {
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
+ gpio@20 {
+ compatible = "nxp,pca9506";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@21 {
+ compatible = "nxp,pca9506";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9506";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@23 {
+ compatible = "nxp,pca9506";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
power-sensor@40 {
compatible = "adi,adm1281";
reg = <0x40>;
@@ -193,6 +221,34 @@ mctp@10 {
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
+ gpio@20 {
+ compatible = "nxp,pca9506";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@21 {
+ compatible = "nxp,pca9506";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9506";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@23 {
+ compatible = "nxp,pca9506";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
power-sensor@40 {
compatible = "adi,adm1281";
reg = <0x40>;
@@ -211,6 +267,34 @@ mctp@10 {
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
+ gpio@20 {
+ compatible = "nxp,pca9506";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@21 {
+ compatible = "nxp,pca9506";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9506";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@23 {
+ compatible = "nxp,pca9506";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
power-sensor@40 {
compatible = "adi,adm1281";
reg = <0x40>;
@@ -229,6 +313,34 @@ mctp@10 {
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
+ gpio@20 {
+ compatible = "nxp,pca9506";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@21 {
+ compatible = "nxp,pca9506";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9506";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@23 {
+ compatible = "nxp,pca9506";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
power-sensor@40 {
compatible = "adi,adm1281";
reg = <0x40>;
@@ -247,6 +359,34 @@ mctp@10 {
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
+ gpio@20 {
+ compatible = "nxp,pca9506";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@21 {
+ compatible = "nxp,pca9506";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9506";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@23 {
+ compatible = "nxp,pca9506";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
power-sensor@40 {
compatible = "adi,adm1281";
reg = <0x40>;
@@ -265,6 +405,34 @@ mctp@10 {
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
+ gpio@20 {
+ compatible = "nxp,pca9506";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@21 {
+ compatible = "nxp,pca9506";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9506";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@23 {
+ compatible = "nxp,pca9506";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
power-sensor@40 {
compatible = "adi,adm1281";
reg = <0x40>;
@@ -283,6 +451,34 @@ mctp@10 {
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
+ gpio@20 {
+ compatible = "nxp,pca9506";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@21 {
+ compatible = "nxp,pca9506";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9506";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@23 {
+ compatible = "nxp,pca9506";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
power-sensor@40 {
compatible = "adi,adm1281";
reg = <0x40>;
@@ -301,6 +497,34 @@ mctp@10 {
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
+ gpio@20 {
+ compatible = "nxp,pca9506";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@21 {
+ compatible = "nxp,pca9506";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9506";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@23 {
+ compatible = "nxp,pca9506";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
power-sensor@40 {
compatible = "adi,adm1281";
reg = <0x40>;
@@ -683,6 +907,33 @@ rtc@6f {
&i2c13 {
status = "okay";
bus-frequency = <400000>;
+ gpio@20 {
+ compatible = "nxp,pca9506";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@21 {
+ compatible = "nxp,pca9506";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9506";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@23 {
+ compatible = "nxp,pca9506";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
};
&i2c14 {
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v5 07/21] ARM: dts: aspeed: yosemite4: Add gpio pca9506
2024-01-31 8:41 ` [PATCH v5 07/21] ARM: dts: aspeed: yosemite4: Add gpio pca9506 Delphine CC Chiu
@ 2024-02-01 5:35 ` Andrew Jeffery
0 siblings, 0 replies; 37+ messages in thread
From: Andrew Jeffery @ 2024-02-01 5:35 UTC (permalink / raw)
To: Delphine CC Chiu, patrick, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Joel Stanley
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel
On Wed, 2024-01-31 at 16:41 +0800, Delphine CC Chiu wrote:
> Add gpio pca9506 I/O expander for yv4 use
Use for what? It seems like there's a pattern to the additions, it
might be good to discuss that briefly?
Andrew
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v5 08/21] ARM: dts: aspeed: yosemite4: Remove space for adm1272 compatible
2024-01-31 8:41 [PATCH v5 00/21] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
` (6 preceding siblings ...)
2024-01-31 8:41 ` [PATCH v5 07/21] ARM: dts: aspeed: yosemite4: Add gpio pca9506 Delphine CC Chiu
@ 2024-01-31 8:41 ` Delphine CC Chiu
2024-02-01 4:28 ` Andrew Jeffery
2024-01-31 8:41 ` [PATCH v5 09/21] ARM: dts: aspeed: yosemite4: Enable interrupt setting for pca9555 Delphine CC Chiu
` (12 subsequent siblings)
20 siblings, 1 reply; 37+ messages in thread
From: Delphine CC Chiu @ 2024-01-31 8:41 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Remove space for adm1272 compatible
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index b1775b5a6782..cbf385e72e57 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -821,12 +821,12 @@ imux29: i2c@1 {
&i2c11 {
status = "okay";
power-sensor@10 {
- compatible = "adi, adm1272";
+ compatible = "adi,adm1272";
reg = <0x10>;
};
power-sensor@12 {
- compatible = "adi, adm1272";
+ compatible = "adi,adm1272";
reg = <0x12>;
};
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v5 08/21] ARM: dts: aspeed: yosemite4: Remove space for adm1272 compatible
2024-01-31 8:41 ` [PATCH v5 08/21] ARM: dts: aspeed: yosemite4: Remove space for adm1272 compatible Delphine CC Chiu
@ 2024-02-01 4:28 ` Andrew Jeffery
0 siblings, 0 replies; 37+ messages in thread
From: Andrew Jeffery @ 2024-02-01 4:28 UTC (permalink / raw)
To: Delphine CC Chiu, patrick, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Joel Stanley
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel
On Wed, 2024-01-31 at 16:41 +0800, Delphine CC Chiu wrote:
> Remove space for adm1272 compatible
>
> Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
Slightly surprised the original submission didn't trigger a report from
the build bots.
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v5 09/21] ARM: dts: aspeed: yosemite4: Enable interrupt setting for pca9555
2024-01-31 8:41 [PATCH v5 00/21] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
` (7 preceding siblings ...)
2024-01-31 8:41 ` [PATCH v5 08/21] ARM: dts: aspeed: yosemite4: Remove space for adm1272 compatible Delphine CC Chiu
@ 2024-01-31 8:41 ` Delphine CC Chiu
2024-02-01 4:33 ` Andrew Jeffery
2024-01-31 8:41 ` [PATCH v5 10/21] ARM: dts: aspeed: yosemite4: Add power sensor for power module reading Delphine CC Chiu
` (11 subsequent siblings)
20 siblings, 1 reply; 37+ messages in thread
From: Delphine CC Chiu @ 2024-01-31 8:41 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Enable interrupt setting for pca9555
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
Changelog:
- v4
- Revise device node name
- v1
- enable interrupt setting for pca9555
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 56 +++++++++++++++++--
1 file changed, 52 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index cbf385e72e57..4b23e467690f 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -832,30 +832,78 @@ power-sensor@12 {
gpio@20 {
compatible = "nxp,pca9555";
- reg = <0x20>;
+ pinctrl-names = "default";
gpio-controller;
#gpio-cells = <2>;
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <98 IRQ_TYPE_LEVEL_LOW>;
+ gpio-line-names =
+ "P48V-OCP-GPIO1","P48V-OCP-GPIO2",
+ "P48V-OCP-GPIO3","FAN-BOARD-0-REVISION-0-R",
+ "FAN-BOARD-0-REVISION-1-R","FAN-BOARD-1-REVISION-0-R",
+ "FAN-BOARD-1-REVISION-1-R","RST-MUX-R-N",
+ "RST-LED-CONTROL-FAN-BOARD-0-N","RST-LED-CONTROL-FAN-BOARD-1-N",
+ "RST-IOEXP-FAN-BOARD-0-N","RST-IOEXP-FAN-BOARD-1-N",
+ "PWRGD-LOAD-SWITCH-FAN-BOARD-0-R","PWRGD-LOAD-SWITCH-FAN-BOARD-1-R",
+ "","";
};
gpio@21 {
compatible = "nxp,pca9555";
- reg = <0x21>;
+ pinctrl-names = "default";
gpio-controller;
#gpio-cells = <2>;
+ reg = <0x21>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <98 IRQ_TYPE_LEVEL_LOW>;
+ gpio-line-names =
+ "HSC-OCP-SLOT-ODD-GPIO1","HSC-OCP-SLOT-ODD-GPIO2",
+ "HSC-OCP-SLOT-ODD-GPIO3","HSC-OCP-SLOT-EVEN-GPIO1",
+ "HSC-OCP-SLOT-EVEN-GPIO2","HSC-OCP-SLOT-EVEN-GPIO3",
+ "ADC-TYPE-0-R","ADC-TYPE-1-R",
+ "MEDUSA-BOARD-REV-0","MEDUSA-BOARD-REV-1",
+ "MEDUSA-BOARD-REV-2","MEDUSA-BOARD-TYPE",
+ "DELTA-MODULE-TYPE","P12V-HSC-TYPE",
+ "","";
};
gpio@22 {
compatible = "nxp,pca9555";
- reg = <0x22>;
+ pinctrl-names = "default";
gpio-controller;
#gpio-cells = <2>;
+ reg = <0x22>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <98 IRQ_TYPE_LEVEL_LOW>;
+ gpio-line-names =
+ "CARD-TYPE-SLOT1","CARD-TYPE-SLOT2",
+ "CARD-TYPE-SLOT3","CARD-TYPE-SLOT4",
+ "CARD-TYPE-SLOT5","CARD-TYPE-SLOT6",
+ "CARD-TYPE-SLOT7","CARD-TYPE-SLOT8",
+ "OC-P48V-HSC-0-N","FLT-P48V-HSC-0-N",
+ "OC-P48V-HSC-1-N","FLT-P48V-HSC-1-N",
+ "EN-P48V-AUX-0","EN-P48V-AUX-1",
+ "PWRGD-P12V-AUX-0","PWRGD-P12V-AUX-1";
};
gpio@23 {
compatible = "nxp,pca9555";
- reg = <0x23>;
+ pinctrl-names = "default";
gpio-controller;
#gpio-cells = <2>;
+ reg = <0x23>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <98 IRQ_TYPE_LEVEL_LOW>;
+ gpio-line-names =
+ "HSC1-ALERT1-R-N","HSC2-ALERT1-R-N",
+ "HSC3-ALERT1-R-N","HSC4-ALERT1-R-N",
+ "HSC5-ALERT1-R-N","HSC6-ALERT1-R-N",
+ "HSC7-ALERT1-R-N","HSC8-ALERT1-R-N",
+ "HSC1-ALERT2-R-N","HSC2-ALERT2-R-N",
+ "HSC3-ALERT2-R-N","HSC4-ALERT2-R-N",
+ "HSC5-ALERT2-R-N","HSC6-ALERT2-R-N",
+ "HSC7-ALERT2-R-N","HSC8-ALERT2-R-N";
};
temperature-sensor@48 {
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v5 09/21] ARM: dts: aspeed: yosemite4: Enable interrupt setting for pca9555
2024-01-31 8:41 ` [PATCH v5 09/21] ARM: dts: aspeed: yosemite4: Enable interrupt setting for pca9555 Delphine CC Chiu
@ 2024-02-01 4:33 ` Andrew Jeffery
0 siblings, 0 replies; 37+ messages in thread
From: Andrew Jeffery @ 2024-02-01 4:33 UTC (permalink / raw)
To: Delphine CC Chiu, patrick, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Joel Stanley
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel
On Wed, 2024-01-31 at 16:41 +0800, Delphine CC Chiu wrote:
> Enable interrupt setting for pca9555
>
> Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
> ---
> Changelog:
> - v4
> - Revise device node name
> - v1
> - enable interrupt setting for pca9555
> ---
> .../aspeed/aspeed-bmc-facebook-yosemite4.dts | 56 +++++++++++++++++--
> 1 file changed, 52 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> index cbf385e72e57..4b23e467690f 100644
> --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> @@ -832,30 +832,78 @@ power-sensor@12 {
>
> gpio@20 {
> compatible = "nxp,pca9555";
> - reg = <0x20>;
> + pinctrl-names = "default";
> gpio-controller;
> #gpio-cells = <2>;
> + reg = <0x20>;
> + interrupt-parent = <&gpio0>;
> + interrupts = <98 IRQ_TYPE_LEVEL_LOW>;
> + gpio-line-names =
> + "P48V-OCP-GPIO1","P48V-OCP-GPIO2",
> + "P48V-OCP-GPIO3","FAN-BOARD-0-REVISION-0-R",
> + "FAN-BOARD-0-REVISION-1-R","FAN-BOARD-1-REVISION-0-R",
> + "FAN-BOARD-1-REVISION-1-R","RST-MUX-R-N",
> + "RST-LED-CONTROL-FAN-BOARD-0-N","RST-LED-CONTROL-FAN-BOARD-1-N",
> + "RST-IOEXP-FAN-BOARD-0-N","RST-IOEXP-FAN-BOARD-1-N",
> + "PWRGD-LOAD-SWITCH-FAN-BOARD-0-R","PWRGD-LOAD-SWITCH-FAN-BOARD-1-R",
> + "","";
Perhaps the addition of the line names should go in a separate patch?
They seem unrelated to the interrupt configuration. The query applies
to the hunks below as well.
> };
>
> gpio@21 {
> compatible = "nxp,pca9555";
> - reg = <0x21>;
> + pinctrl-names = "default";
> gpio-controller;
> #gpio-cells = <2>;
> + reg = <0x21>;
> + interrupt-parent = <&gpio0>;
> + interrupts = <98 IRQ_TYPE_LEVEL_LOW>;
> + gpio-line-names =
> + "HSC-OCP-SLOT-ODD-GPIO1","HSC-OCP-SLOT-ODD-GPIO2",
> + "HSC-OCP-SLOT-ODD-GPIO3","HSC-OCP-SLOT-EVEN-GPIO1",
> + "HSC-OCP-SLOT-EVEN-GPIO2","HSC-OCP-SLOT-EVEN-GPIO3",
> + "ADC-TYPE-0-R","ADC-TYPE-1-R",
> + "MEDUSA-BOARD-REV-0","MEDUSA-BOARD-REV-1",
> + "MEDUSA-BOARD-REV-2","MEDUSA-BOARD-TYPE",
> + "DELTA-MODULE-TYPE","P12V-HSC-TYPE",
> + "","";
> };
>
> gpio@22 {
> compatible = "nxp,pca9555";
> - reg = <0x22>;
> + pinctrl-names = "default";
> gpio-controller;
> #gpio-cells = <2>;
> + reg = <0x22>;
> + interrupt-parent = <&gpio0>;
> + interrupts = <98 IRQ_TYPE_LEVEL_LOW>;
> + gpio-line-names =
> + "CARD-TYPE-SLOT1","CARD-TYPE-SLOT2",
> + "CARD-TYPE-SLOT3","CARD-TYPE-SLOT4",
> + "CARD-TYPE-SLOT5","CARD-TYPE-SLOT6",
> + "CARD-TYPE-SLOT7","CARD-TYPE-SLOT8",
> + "OC-P48V-HSC-0-N","FLT-P48V-HSC-0-N",
> + "OC-P48V-HSC-1-N","FLT-P48V-HSC-1-N",
> + "EN-P48V-AUX-0","EN-P48V-AUX-1",
> + "PWRGD-P12V-AUX-0","PWRGD-P12V-AUX-1";
> };
>
> gpio@23 {
> compatible = "nxp,pca9555";
> - reg = <0x23>;
> + pinctrl-names = "default";
> gpio-controller;
> #gpio-cells = <2>;
> + reg = <0x23>;
> + interrupt-parent = <&gpio0>;
> + interrupts = <98 IRQ_TYPE_LEVEL_LOW>;
Just confirming the interrupt lines from the expanders are all wired up
to the one GPIO input pin on the BMC?
Andrew
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v5 10/21] ARM: dts: aspeed: yosemite4: Add power sensor for power module reading
2024-01-31 8:41 [PATCH v5 00/21] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
` (8 preceding siblings ...)
2024-01-31 8:41 ` [PATCH v5 09/21] ARM: dts: aspeed: yosemite4: Enable interrupt setting for pca9555 Delphine CC Chiu
@ 2024-01-31 8:41 ` Delphine CC Chiu
2024-02-01 4:34 ` Andrew Jeffery
2024-01-31 8:41 ` [PATCH v5 11/21] ARM: dts: aspeed: yosemite4: Add eeprom for yosemite4 use Delphine CC Chiu
` (10 subsequent siblings)
20 siblings, 1 reply; 37+ messages in thread
From: Delphine CC Chiu @ 2024-01-31 8:41 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Add power sensor for power module reading
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 25 +++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index 4b23e467690f..e8d7eb7ff568 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -906,6 +906,11 @@ gpio@23 {
"HSC7-ALERT2-R-N","HSC8-ALERT2-R-N";
};
+ power-sensor@40 {
+ compatible = "mps,mp5023";
+ reg = <0x40>;
+ };
+
temperature-sensor@48 {
compatible = "ti,tmp75";
reg = <0x48>;
@@ -930,6 +935,26 @@ eeprom@54 {
compatible = "atmel,24c256";
reg = <0x54>;
};
+
+ power-sensor@62 {
+ compatible = "pmbus";
+ reg = <0x62>;
+ };
+
+ power-sensor@64 {
+ compatible = "pmbus";
+ reg = <0x64>;
+ };
+
+ power-sensor@65 {
+ compatible = "pmbus";
+ reg = <0x65>;
+ };
+
+ power-sensor@68 {
+ compatible = "pmbus";
+ reg = <0x68>;
+ };
};
&i2c12 {
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v5 10/21] ARM: dts: aspeed: yosemite4: Add power sensor for power module reading
2024-01-31 8:41 ` [PATCH v5 10/21] ARM: dts: aspeed: yosemite4: Add power sensor for power module reading Delphine CC Chiu
@ 2024-02-01 4:34 ` Andrew Jeffery
0 siblings, 0 replies; 37+ messages in thread
From: Andrew Jeffery @ 2024-02-01 4:34 UTC (permalink / raw)
To: Delphine CC Chiu, patrick, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Joel Stanley
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel
On Wed, 2024-01-31 at 16:41 +0800, Delphine CC Chiu wrote:
> Add power sensor for power module reading
It would be nice if we had a bit more of a description about e.g. what
they're monitoring.
Andrew
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v5 11/21] ARM: dts: aspeed: yosemite4: Add eeprom for yosemite4 use
2024-01-31 8:41 [PATCH v5 00/21] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
` (9 preceding siblings ...)
2024-01-31 8:41 ` [PATCH v5 10/21] ARM: dts: aspeed: yosemite4: Add power sensor for power module reading Delphine CC Chiu
@ 2024-01-31 8:41 ` Delphine CC Chiu
2024-02-01 5:45 ` Andrew Jeffery
2024-01-31 8:41 ` [PATCH v5 12/21] ARM: dts: aspeed: yosemite4: Remove temperature sensor for yosemite4 schematic change Delphine CC Chiu
` (9 subsequent siblings)
20 siblings, 1 reply; 37+ messages in thread
From: Delphine CC Chiu @ 2024-01-31 8:41 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Add eeprom for yosemite4 use
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index e8d7eb7ff568..f00df378a371 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -932,7 +932,7 @@ temperature-sensor@4b {
};
eeprom@54 {
- compatible = "atmel,24c256";
+ compatible = "atmel,24c128";
reg = <0x54>;
};
@@ -971,6 +971,11 @@ eeprom@50 {
reg = <0x50>;
};
+ eeprom@54 {
+ compatible = "atmel,24c64";
+ reg = <0x54>;
+ };
+
rtc@6f {
compatible = "nuvoton,nct3018y";
reg = <0x6f>;
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v5 11/21] ARM: dts: aspeed: yosemite4: Add eeprom for yosemite4 use
2024-01-31 8:41 ` [PATCH v5 11/21] ARM: dts: aspeed: yosemite4: Add eeprom for yosemite4 use Delphine CC Chiu
@ 2024-02-01 5:45 ` Andrew Jeffery
0 siblings, 0 replies; 37+ messages in thread
From: Andrew Jeffery @ 2024-02-01 5:45 UTC (permalink / raw)
To: Delphine CC Chiu, patrick, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Joel Stanley
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel
On Wed, 2024-01-31 at 16:41 +0800, Delphine CC Chiu wrote:
> Add eeprom for yosemite4 use
>
> Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
> ---
> arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> index e8d7eb7ff568..f00df378a371 100644
> --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> @@ -932,7 +932,7 @@ temperature-sensor@4b {
> };
>
> eeprom@54 {
> - compatible = "atmel,24c256";
> + compatible = "atmel,24c128";
This is changing an existing eeprom, not adding a new one - contrary to
the commit message. It probably should be in a separate patch?
Presumably this is also motivated by the change in the schematics? Some
explanation would be helpful.
I'm half wondering whether it would have been easier to add a separate
DTS for the new version of the schematic rather than make all these
piecemeal changes.
Andrew
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v5 12/21] ARM: dts: aspeed: yosemite4: Remove temperature sensor for yosemite4 schematic change
2024-01-31 8:41 [PATCH v5 00/21] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
` (10 preceding siblings ...)
2024-01-31 8:41 ` [PATCH v5 11/21] ARM: dts: aspeed: yosemite4: Add eeprom for yosemite4 use Delphine CC Chiu
@ 2024-01-31 8:41 ` Delphine CC Chiu
2024-02-01 5:38 ` Andrew Jeffery
2024-01-31 8:41 ` [PATCH v5 13/21] ARM: dts: aspeed: yosemite4: Revise adc128d818 adc mode " Delphine CC Chiu
` (8 subsequent siblings)
20 siblings, 1 reply; 37+ messages in thread
From: Delphine CC Chiu @ 2024-01-31 8:41 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Remove temperature sensor for yosemite4 schematic change
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index f00df378a371..bb4cba8f057e 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -921,16 +921,6 @@ temperature-sensor@49 {
reg = <0x49>;
};
- temperature-sensor@4a {
- compatible = "ti,tmp75";
- reg = <0x4a>;
- };
-
- temperature-sensor@4b {
- compatible = "ti,tmp75";
- reg = <0x4b>;
- };
-
eeprom@54 {
compatible = "atmel,24c128";
reg = <0x54>;
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v5 12/21] ARM: dts: aspeed: yosemite4: Remove temperature sensor for yosemite4 schematic change
2024-01-31 8:41 ` [PATCH v5 12/21] ARM: dts: aspeed: yosemite4: Remove temperature sensor for yosemite4 schematic change Delphine CC Chiu
@ 2024-02-01 5:38 ` Andrew Jeffery
0 siblings, 0 replies; 37+ messages in thread
From: Andrew Jeffery @ 2024-02-01 5:38 UTC (permalink / raw)
To: Delphine CC Chiu, patrick, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Joel Stanley
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel
On Wed, 2024-01-31 at 16:41 +0800, Delphine CC Chiu wrote:
> Remove temperature sensor for yosemite4 schematic change
Presumably the schematics are versioned. Which version is the patch
moving the DTS from, and which is it moving the DTS to?
Andrew
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v5 13/21] ARM: dts: aspeed: yosemite4: Revise adc128d818 adc mode for yosemite4 schematic change
2024-01-31 8:41 [PATCH v5 00/21] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
` (11 preceding siblings ...)
2024-01-31 8:41 ` [PATCH v5 12/21] ARM: dts: aspeed: yosemite4: Remove temperature sensor for yosemite4 schematic change Delphine CC Chiu
@ 2024-01-31 8:41 ` Delphine CC Chiu
2024-01-31 8:41 ` [PATCH v5 14/21] ARM: dts: aspeed: yosemite4: Revise ina233 config " Delphine CC Chiu
` (7 subsequent siblings)
20 siblings, 0 replies; 37+ messages in thread
From: Delphine CC Chiu @ 2024-01-31 8:41 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Revise adc128d818 adc mode for yosemite4 schematic change
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index bb4cba8f057e..4cf4b0ca1024 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -1010,19 +1010,19 @@ &i2c14 {
adc@1d {
compatible = "ti,adc128d818";
reg = <0x1d>;
- ti,mode = /bits/ 8 <2>;
+ ti,mode = /bits/ 8 <1>;
};
- adc@35 {
+ adc@36 {
compatible = "ti,adc128d818";
- reg = <0x35>;
- ti,mode = /bits/ 8 <2>;
+ reg = <0x36>;
+ ti,mode = /bits/ 8 <1>;
};
adc@37 {
compatible = "ti,adc128d818";
reg = <0x37>;
- ti,mode = /bits/ 8 <2>;
+ ti,mode = /bits/ 8 <1>;
};
power-sensor@40 {
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH v5 14/21] ARM: dts: aspeed: yosemite4: Revise ina233 config for yosemite4 schematic change
2024-01-31 8:41 [PATCH v5 00/21] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
` (12 preceding siblings ...)
2024-01-31 8:41 ` [PATCH v5 13/21] ARM: dts: aspeed: yosemite4: Revise adc128d818 adc mode " Delphine CC Chiu
@ 2024-01-31 8:41 ` Delphine CC Chiu
2024-01-31 8:41 ` [PATCH v5 15/21] ARM: dts: aspeed: yosemite4: Remove idle state setting for yosemite4 NIC connection Delphine CC Chiu
` (6 subsequent siblings)
20 siblings, 0 replies; 37+ messages in thread
From: Delphine CC Chiu @ 2024-01-31 8:41 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Revise ina233 config for yosemite4 schematic change
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 20 ++++++++++++++-----
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index 4cf4b0ca1024..f0e93c74003a 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -1026,28 +1026,38 @@ adc@37 {
};
power-sensor@40 {
- compatible = "ti,ina230";
+ compatible = "ti,ina233";
reg = <0x40>;
+ resistor-calibration = /bits/ 16 <0x0a00>;
+ current-lsb= /bits/ 16 <0x0001>;
};
power-sensor@41 {
- compatible = "ti,ina230";
+ compatible = "ti,ina233";
reg = <0x41>;
+ resistor-calibration = /bits/ 16 <0x0a00>;
+ current-lsb= /bits/ 16 <0x0001>;
};
power-sensor@42 {
- compatible = "ti,ina230";
+ compatible = "ti,ina233";
reg = <0x42>;
+ resistor-calibration = /bits/ 16 <0x0a00>;
+ current-lsb= /bits/ 16 <0x0001>;
};
power-sensor@43 {
- compatible = "ti,ina230";
+ compatible = "ti,ina233";
reg = <0x43>;
+ resistor-calibration = /bits/ 16 <0x0a00>;
+ current-lsb= /bits/ 16 <0x0001>;
};
power-sensor@44 {
- compatible = "ti,ina230";
+ compatible = "ti,ina233";
reg = <0x44>;
+ resistor-calibration = /bits/ 16 <0x0a00>;
+ current-lsb= /bits/ 16 <0x0001>;
};
temperature-sensor@4e {
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH v5 15/21] ARM: dts: aspeed: yosemite4: Remove idle state setting for yosemite4 NIC connection
2024-01-31 8:41 [PATCH v5 00/21] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
` (13 preceding siblings ...)
2024-01-31 8:41 ` [PATCH v5 14/21] ARM: dts: aspeed: yosemite4: Revise ina233 config " Delphine CC Chiu
@ 2024-01-31 8:41 ` Delphine CC Chiu
2024-02-01 5:47 ` Andrew Jeffery
2024-01-31 8:41 ` [PATCH v5 16/21] ARM: dts: aspeed: yosemite4: Initialize bmc gpio state Delphine CC Chiu
` (5 subsequent siblings)
20 siblings, 1 reply; 37+ messages in thread
From: Delphine CC Chiu @ 2024-01-31 8:41 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Remove idle state setting for yosemite4 NIC connection
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index f0e93c74003a..6d5710e5753c 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -1227,7 +1227,6 @@ mctp@10 {
i2c-mux@72 {
compatible = "nxp,pca9544";
- i2c-mux-idle-disconnect;
reg = <0x72>;
imux24: i2c@0 {
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v5 15/21] ARM: dts: aspeed: yosemite4: Remove idle state setting for yosemite4 NIC connection
2024-01-31 8:41 ` [PATCH v5 15/21] ARM: dts: aspeed: yosemite4: Remove idle state setting for yosemite4 NIC connection Delphine CC Chiu
@ 2024-02-01 5:47 ` Andrew Jeffery
0 siblings, 0 replies; 37+ messages in thread
From: Andrew Jeffery @ 2024-02-01 5:47 UTC (permalink / raw)
To: Delphine CC Chiu, patrick, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Joel Stanley
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel
On Wed, 2024-01-31 at 16:41 +0800, Delphine CC Chiu wrote:
> Remove idle state setting for yosemite4 NIC connection
But why? Is this fixing a bug? What is the motivation?
Andrew
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v5 16/21] ARM: dts: aspeed: yosemite4: Initialize bmc gpio state
2024-01-31 8:41 [PATCH v5 00/21] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
` (14 preceding siblings ...)
2024-01-31 8:41 ` [PATCH v5 15/21] ARM: dts: aspeed: yosemite4: Remove idle state setting for yosemite4 NIC connection Delphine CC Chiu
@ 2024-01-31 8:41 ` Delphine CC Chiu
2024-02-01 5:49 ` Andrew Jeffery
2024-01-31 8:41 ` [PATCH v5 17/21] ARM: dts: aspeed: yosemite4: Revise mx31790 fan tach config Delphine CC Chiu
` (4 subsequent siblings)
20 siblings, 1 reply; 37+ messages in thread
From: Delphine CC Chiu @ 2024-01-31 8:41 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Initialize bmc gpio state
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
Changelog:
- v4
- Rename gpio-line-names
- v3
- Add patch for revising gpio name
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 192 ++++++++++++++++++
1 file changed, 192 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index 6d5710e5753c..bce739f2a081 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -1271,6 +1271,7 @@ temperature-sensor@1f {
};
};
+
&adc0 {
ref_voltage = <2500>;
status = "okay";
@@ -1298,3 +1299,194 @@ &ehci1 {
&uhci {
status = "okay";
};
+
+&sgpiom0 {
+ status = "okay";
+ ngpios = <128>;
+ bus-frequency = <48000>;
+};
+
+&gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpiu2_default &pinctrl_gpiu3_default
+ &pinctrl_gpiu4_default &pinctrl_gpiu6_default>;
+ gpio-line-names =
+ /*A0-A7*/ "","","","","","","","",
+ /*B0-B7*/ "FLT-HSC-SERVER-SLOT8-N","AC-ON-OFF-BTN-CPLD-SLOT5-N",
+ "PWRGD-SLOT1-STBY","PWRGD-SLOT2-STBY",
+ "PWRGD-SLOT3-STBY","PWRGD-SLOT4-STBY","","",
+ /*C0-C7*/ "","","","","FM-NIC0-WAKE-N",
+ "FM-NIC1-WAKE-N","","RST-PCIE-SLOT2-N",
+ /*D0-D7*/ "","","","","","","","",
+ /*E0-E7*/ "PRSNT-NIC1-N","PRSNT-NIC2-N","","RST-PCIE-SLOT1-N",
+ "","","","",
+ /*F0-F7*/ "FM-RESBTN-SLOT1-BMC-N","FM-RESBTN-SLOT2-BMC-N",
+ "FM-RESBTN-SLOT3-BMC-N","FM-RESBTN-SLOT4-BMC-N",
+ "PRSNT-SB-SLOT1-N","PRSNT-SB-SLOT2-N",
+ "PRSNT-SB-SLOT3-N","PRSNT-SB-SLOT4-N",
+ /*G0-G7*/ "","","","","","","","",
+ /*H0-H7*/ "","","","","","","","",
+ /*I0-I7*/ "","","","","","ALT-MEDUSA-ADC-N",
+ "ALT-SMB-BMC-CPLD2-N",
+ "INT-SPIDER-ADC-R-N",
+ /*J0-J7*/ "","","","","","","","",
+ /*K0-K7*/ "","","","","","","","",
+ /*L0-L7*/ "","","","","","","ALT-MEDUSA-P12V-EFUSE-N","",
+ /*M0-M7*/ "EN-NIC0-POWER-BMC-R","EN-NIC1-POWER-BMC-R",
+ "INT-MEDUSA-IOEXP-TEMP-N","PRSNT-NIC3-N",
+ "INT-SMB-BMC-SLOT1-4-BMC-N",
+ "AC-ON-OFF-BTN-CPLD-SLOT6-N","","",
+ /*N0-N7*/ "FLT-HSC-SERVER-SLOT1-N","FLT-HSC-SERVER-SLOT2-N",
+ "FLT-HSC-SERVER-SLOT3-N","FLT-HSC-SERVER-SLOT4-N",
+ "FM-BMC-READY-R2","RST-SMB-NIC0-R-N","","",
+ /*O0-O7*/ "AC-ON-OFF-BTN-CPLD-SLOT8-N","RST-SMB-NIC1-R-N",
+ "RST-SMB-NIC2-R-N","RST-SMB-NIC3-R-N",
+ "","","","",
+ /*P0-P7*/ "ALT-SMB-BMC-CPLD1-N","'BTN-BMC-R2-N",
+ "EN-P3V-BAT-SCALED-R","PWRGD-P5V-USB-BMC",
+ "FM-BMC-RTCRST-R","RST-USB-HUB-R-N",
+ "FLAG-P5V-USB-BMC-N","",
+ /*Q0-Q7*/ "AC-ON-OFF-BTN-CPLD-SLOT1-N","AC-ON-OFF-BTN-CPLD-SLOT2-N",
+ "AC-ON-OFF-BTN-CPLD-SLOT3-N","AC-ON-OFF-BTN-CPLD-SLOT4-N",
+ "PRSNT-SB-SLOT5-N","PRSNT-SB-SLOT6-N",
+ "PRSNT-SB-SLOT7-N","PRSNT-SB-SLOT8-N",
+ /*R0-R7*/ "AC-ON-OFF-BTN-CPLD-SLOT7-N","INT-SMB-BMC-SLOT5-8-BMC-N",
+ "FM-PWRBRK-NIC-BMC-R2","RST-PCIE-SLOT4-N",
+ "RST-PCIE-SLOT5-N","RST-PCIE-SLOT6-N",
+ "RST-PCIE-SLOT7-N","RST-PCIE-SLOT8-N",
+ /*S0-S7*/ "FM-NIC2-WAKE-N","FM-NIC3-WAKE-N",
+ "EN-NIC3-POWER-BMC-R","SEL-BMC-JTAG-MUX-R",
+ "","ALT-P12V-AUX-N","FAST-PROCHOT-N",
+ "SPI-WP-DISABLE-STATUS-R-N",
+ /*T0-T7*/ "","","","","","","","",
+ /*U0-U7*/ "","","RST-PCIE-SLOT3-N","",
+ "","PRSNT-NIC0-N","","",
+ /*V0-V7*/ "FM-RESBTN-SLOT5-BMC-N","FM-RESBTN-SLOT6-BMC-N",
+ "FM-RESBTN-SLOT7-BMC-N","FM-RESBTN-SLOT8-BMC-N",
+ "","","","",
+ /*W0-W7*/ "PRSNT-TPM-BMC-N","PRSNT-OCP-DEBUG-BMC-N","ALT-TEMP-BMC-N","ALT-RTC-BMC-N",
+ "","","","",
+ /*X0-X7*/ "","LT-HSC-SERVER-SLOT6-N","FLT-HSC-SERVER-SLOT7-N","","","",
+ "PWRGD-SLOT5-STBY","PWRGD-SLOT6-STBY",
+ /*Y0-Y7*/ "","","SPI-LOCK-REQ-BMC-N","PWRGD-SLOT7-STBY",
+ "","","EN-NIC2-POWER-BMC-R","",
+ /*Z0-Z7*/ "EN-P5V-USB-CPLD-R","'FLT-HSC-SERVER-SLOT5-N",
+ "PWRGD-SLOT8-STBY","","","","","";
+
+ pin_gpio_b4 {
+ gpios = <ASPEED_GPIO(B, 4) GPIO_ACTIVE_HIGH>;
+ input;
+ };
+ pin_gpio_b5 {
+ gpios = <ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
+ input;
+ };
+ pin_gpio_f0 {
+ gpios = <ASPEED_GPIO(F, 0) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f1 {
+ gpios = <ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f2 {
+ gpios = <ASPEED_GPIO(F, 2) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f3 {
+ gpios = <ASPEED_GPIO(F, 3) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f4 {
+ gpios = <ASPEED_GPIO(F, 4) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f5 {
+ gpios = <ASPEED_GPIO(F, 5) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f6 {
+ gpios = <ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f7 {
+ gpios = <ASPEED_GPIO(F, 7) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_l6 {
+ gpios = <ASPEED_GPIO(L, 6) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_l7 {
+ gpios = <ASPEED_GPIO(L, 7) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_s0 {
+ gpios = <ASPEED_GPIO(S, 0) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_s1 {
+ gpios = <ASPEED_GPIO(S, 1) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_v0 {
+ gpios = <ASPEED_GPIO(V, 0) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_v1 {
+ gpios = <ASPEED_GPIO(V, 1) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_v2 {
+ gpios = <ASPEED_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_v3 {
+ gpios = <ASPEED_GPIO(V, 3) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w0 {
+ gpios = <ASPEED_GPIO(W, 0) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w1 {
+ gpios = <ASPEED_GPIO(W, 1) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w2 {
+ gpios = <ASPEED_GPIO(W, 2) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w3 {
+ gpios = <ASPEED_GPIO(W, 3) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w4 {
+ gpios = <ASPEED_GPIO(W, 4) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w5 {
+ gpios = <ASPEED_GPIO(W, 5) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w6 {
+ gpios = <ASPEED_GPIO(W, 6) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w7 {
+ gpios = <ASPEED_GPIO(W, 7) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_z3 {
+ gpios = <ASPEED_GPIO(Z, 3) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_z4 {
+ gpios = <ASPEED_GPIO(Z, 4) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_z5 {
+ gpios = <ASPEED_GPIO(Z, 5) GPIO_ACTIVE_LOW>;
+ input;
+ };
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v5 16/21] ARM: dts: aspeed: yosemite4: Initialize bmc gpio state
2024-01-31 8:41 ` [PATCH v5 16/21] ARM: dts: aspeed: yosemite4: Initialize bmc gpio state Delphine CC Chiu
@ 2024-02-01 5:49 ` Andrew Jeffery
0 siblings, 0 replies; 37+ messages in thread
From: Andrew Jeffery @ 2024-02-01 5:49 UTC (permalink / raw)
To: Delphine CC Chiu, patrick, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Joel Stanley
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel
On Wed, 2024-01-31 at 16:41 +0800, Delphine CC Chiu wrote:
> Initialize bmc gpio state
Why is it important to specify this in the devicetree? What's the
motivation?
Andrew
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v5 17/21] ARM: dts: aspeed: yosemite4: Revise mx31790 fan tach config
2024-01-31 8:41 [PATCH v5 00/21] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
` (15 preceding siblings ...)
2024-01-31 8:41 ` [PATCH v5 16/21] ARM: dts: aspeed: yosemite4: Initialize bmc gpio state Delphine CC Chiu
@ 2024-01-31 8:41 ` Delphine CC Chiu
2024-01-31 8:41 ` [PATCH v5 18/21] ARM: dts: aspeed: yosemite4: add mctp config for NIC Delphine CC Chiu
` (3 subsequent siblings)
20 siblings, 0 replies; 37+ messages in thread
From: Delphine CC Chiu @ 2024-01-31 8:41 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Revise fan tach config for max31790 driver change
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 48 +++++++++++++++++--
1 file changed, 44 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index bce739f2a081..7c7c9e85bb92 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -1095,8 +1095,18 @@ adc@1f {
pwm@20{
compatible = "maxim,max31790";
- pwm-as-tach = <4 5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x20>;
+ channel@4 {
+ reg = <4>;
+ sensor-type = "TACH";
+ };
+
+ channel@5 {
+ reg = <5>;
+ sensor-type = "TACH";
+ };
};
gpio@22{
@@ -1108,8 +1118,18 @@ gpio@22{
pwm@2f{
compatible = "maxim,max31790";
- pwm-as-tach = <4 5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x2f>;
+ channel@4 {
+ reg = <4>;
+ sensor-type = "TACH";
+ };
+
+ channel@5 {
+ reg = <5>;
+ sensor-type = "TACH";
+ };
};
adc@33 {
@@ -1145,8 +1165,18 @@ adc@1f {
pwm@20{
compatible = "maxim,max31790";
- pwm-as-tach = <4 5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x20>;
+ channel@4 {
+ reg = <4>;
+ sensor-type = "TACH";
+ };
+
+ channel@5 {
+ reg = <5>;
+ sensor-type = "TACH";
+ };
};
gpio@22{
@@ -1158,8 +1188,18 @@ gpio@22{
pwm@2f{
compatible = "maxim,max31790";
- pwm-as-tach = <4 5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x2f>;
+ channel@4 {
+ reg = <4>;
+ sensor-type = "TACH";
+ };
+
+ channel@5 {
+ reg = <5>;
+ sensor-type = "TACH";
+ };
};
adc@33 {
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH v5 18/21] ARM: dts: aspeed: yosemite4: add mctp config for NIC
2024-01-31 8:41 [PATCH v5 00/21] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
` (16 preceding siblings ...)
2024-01-31 8:41 ` [PATCH v5 17/21] ARM: dts: aspeed: yosemite4: Revise mx31790 fan tach config Delphine CC Chiu
@ 2024-01-31 8:41 ` Delphine CC Chiu
2024-02-01 5:53 ` Andrew Jeffery
2024-01-31 8:41 ` [PATCH v5 19/21] ARM: dts: aspeed: yosemite4: support mux to cpld Delphine CC Chiu
` (2 subsequent siblings)
20 siblings, 1 reply; 37+ messages in thread
From: Delphine CC Chiu @ 2024-01-31 8:41 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
add mctp config for NIC
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
Changelog:
- v4
- Revise device node name
- v2
- Add patch for NIC mctp config
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index 7c7c9e85bb92..b9b6fe729cd6 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -1273,40 +1273,64 @@ imux24: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
+ mctp-controller;
temperature-sensor@1f {
compatible = "ti,tmp421";
reg = <0x1f>;
};
+
+ temperature-sensor@3c {
+ compatible = "smsc,emc1403";
+ reg = <0x3c>;
+ };
};
imux25: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
+ mctp-controller;
temperature-sensor@1f {
compatible = "ti,tmp421";
reg = <0x1f>;
};
+
+ temperature-sensor@3c {
+ compatible = "smsc,emc1403";
+ reg = <0x3c>;
+ };
};
imux26: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
+ mctp-controller;
temperature-sensor@1f {
compatible = "ti,tmp421";
reg = <0x1f>;
};
+
+ temperature-sensor@3c {
+ compatible = "smsc,emc1403";
+ reg = <0x3c>;
+ };
};
imux27: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
+ mctp-controller;
temperature-sensor@1f {
compatible = "ti,tmp421";
reg = <0x1f>;
};
+
+ temperature-sensor@3c {
+ compatible = "smsc,emc1403";
+ reg = <0x3c>;
+ };
};
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v5 18/21] ARM: dts: aspeed: yosemite4: add mctp config for NIC
2024-01-31 8:41 ` [PATCH v5 18/21] ARM: dts: aspeed: yosemite4: add mctp config for NIC Delphine CC Chiu
@ 2024-02-01 5:53 ` Andrew Jeffery
0 siblings, 0 replies; 37+ messages in thread
From: Andrew Jeffery @ 2024-02-01 5:53 UTC (permalink / raw)
To: Delphine CC Chiu, patrick, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Joel Stanley
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel
On Wed, 2024-01-31 at 16:41 +0800, Delphine CC Chiu wrote:
> add mctp config for NIC
How does this integrate into the MCTP network(s)? It would be good to
have more of a description.
>
> Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
> ---
> Changelog:
> - v4
> - Revise device node name
> - v2
> - Add patch for NIC mctp config
> ---
> .../aspeed/aspeed-bmc-facebook-yosemite4.dts | 24 +++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> index 7c7c9e85bb92..b9b6fe729cd6 100644
> --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> @@ -1273,40 +1273,64 @@ imux24: i2c@0 {
> #address-cells = <1>;
> #size-cells = <0>;
> reg = <0>;
> + mctp-controller;
> temperature-sensor@1f {
> compatible = "ti,tmp421";
> reg = <0x1f>;
> };
> +
> + temperature-sensor@3c {
> + compatible = "smsc,emc1403";
> + reg = <0x3c>;
> + };
This is unrelated to the MCTP configuration? Same with the other nodes
in the patch.
Andrew
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v5 19/21] ARM: dts: aspeed: yosemite4: support mux to cpld
2024-01-31 8:41 [PATCH v5 00/21] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
` (17 preceding siblings ...)
2024-01-31 8:41 ` [PATCH v5 18/21] ARM: dts: aspeed: yosemite4: add mctp config for NIC Delphine CC Chiu
@ 2024-01-31 8:41 ` Delphine CC Chiu
2024-01-31 8:41 ` [PATCH v5 20/21] ARM: dts: aspeed: yosemite4: support medusa board adc sensors Delphine CC Chiu
2024-01-31 8:41 ` [PATCH v5 21/21] ARM: dts: aspeed: yosemite4: support NIC eeprom Delphine CC Chiu
20 siblings, 0 replies; 37+ messages in thread
From: Delphine CC Chiu @ 2024-01-31 8:41 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Mux pca9544 to cpld was added on EVT HW schematic design,
so add dts setting for devices behind mux pca9544 to cpld
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 64 ++++++++++++++-----
1 file changed, 49 insertions(+), 15 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index b9b6fe729cd6..d97520860f4a 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -36,6 +36,10 @@ aliases {
i2c31 = &imux31;
i2c32 = &imux32;
i2c33 = &imux33;
+ i2c34 = &imux34;
+ i2c35 = &imux35;
+ i2c36 = &imux36;
+ i2c37 = &imux37;
};
chosen {
@@ -951,24 +955,54 @@ &i2c12 {
status = "okay";
bus-frequency = <400000>;
- temperature-sensor@48 {
- compatible = "ti,tmp75";
- reg = <0x48>;
- };
+ i2c-mux@70 {
+ compatible = "nxp,pca9544";
+ i2c-mux-idle-disconnect;
+ reg = <0x70>;
- eeprom@50 {
- compatible = "atmel,24c128";
- reg = <0x50>;
- };
+ imux34: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
- eeprom@54 {
- compatible = "atmel,24c64";
- reg = <0x54>;
- };
+ temperature-sensor@48 {
+ compatible = "ti,tmp75";
+ reg = <0x48>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
- rtc@6f {
- compatible = "nuvoton,nct3018y";
- reg = <0x6f>;
+ eeprom@54 {
+ compatible = "atmel,24c64";
+ reg = <0x54>;
+ };
+
+ rtc@6f {
+ compatible = "nuvoton,nct3018y";
+ reg = <0x6f>;
+ };
+ };
+
+ imux35: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ imux36: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ imux37: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH v5 20/21] ARM: dts: aspeed: yosemite4: support medusa board adc sensors
2024-01-31 8:41 [PATCH v5 00/21] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
` (18 preceding siblings ...)
2024-01-31 8:41 ` [PATCH v5 19/21] ARM: dts: aspeed: yosemite4: support mux to cpld Delphine CC Chiu
@ 2024-01-31 8:41 ` Delphine CC Chiu
2024-01-31 8:41 ` [PATCH v5 21/21] ARM: dts: aspeed: yosemite4: support NIC eeprom Delphine CC Chiu
20 siblings, 0 replies; 37+ messages in thread
From: Delphine CC Chiu @ 2024-01-31 8:41 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Add ina233/ina28 support for medusa board adc sensors
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index d97520860f4a..bb0dc203eafa 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -915,6 +915,19 @@ power-sensor@40 {
reg = <0x40>;
};
+ power-sensor@41 {
+ compatible = "ti,ina233";
+ resistor-calibration = /bits/ 16 <0x0a00>;
+ current-lsb= /bits/ 16 <0x0001>;
+ reg = <0x41>;
+ };
+
+ power-sensor@44 {
+ compatible = "ti,ina238";
+ shunt-resistor = <1000>;
+ reg = <0x44>;
+ };
+
temperature-sensor@48 {
compatible = "ti,tmp75";
reg = <0x48>;
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH v5 21/21] ARM: dts: aspeed: yosemite4: support NIC eeprom
2024-01-31 8:41 [PATCH v5 00/21] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
` (19 preceding siblings ...)
2024-01-31 8:41 ` [PATCH v5 20/21] ARM: dts: aspeed: yosemite4: support medusa board adc sensors Delphine CC Chiu
@ 2024-01-31 8:41 ` Delphine CC Chiu
20 siblings, 0 replies; 37+ messages in thread
From: Delphine CC Chiu @ 2024-01-31 8:41 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Add NIC eeprom devicetree config
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 20 +++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index bb0dc203eafa..8adefa4ec04f 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -1330,6 +1330,11 @@ temperature-sensor@3c {
compatible = "smsc,emc1403";
reg = <0x3c>;
};
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
};
imux25: i2c@1 {
@@ -1346,6 +1351,11 @@ temperature-sensor@3c {
compatible = "smsc,emc1403";
reg = <0x3c>;
};
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
};
imux26: i2c@2 {
@@ -1362,6 +1372,11 @@ temperature-sensor@3c {
compatible = "smsc,emc1403";
reg = <0x3c>;
};
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
};
imux27: i2c@3 {
@@ -1378,6 +1393,11 @@ temperature-sensor@3c {
compatible = "smsc,emc1403";
reg = <0x3c>;
};
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
};
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 37+ messages in thread