From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 939CCC4708D for ; Mon, 5 Dec 2022 16:45:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233242AbiLEQpp (ORCPT ); Mon, 5 Dec 2022 11:45:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41232 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232266AbiLEQpI (ORCPT ); Mon, 5 Dec 2022 11:45:08 -0500 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BCF3220352 for ; Mon, 5 Dec 2022 08:43:49 -0800 (PST) Received: by mail-lf1-x136.google.com with SMTP id x28so2160179lfn.6 for ; Mon, 05 Dec 2022 08:43:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:content-language :references:to:subject:user-agent:mime-version:date:message-id:from :to:cc:subject:date:message-id:reply-to; bh=LwX2JkY0ze5qoxHE8yDK81QnuEc0DDCbSRUUumQxNTo=; b=lnJMduu8Nt+omAPXB//XTa6tUWGuIztSZwaEIGkdVeXyevV84Bus+y9pPw6b+UFv6p 1q4ti5UbmF2o2pX+ELp1wQY6EIoF97miAuLbH/XmcR1HevLlEPq90YHOotFtoBanQGNZ 5nXI+MnP4JVF6kz73pQNxCsoYvcXHlIL2DB8t4lBDnzorqBaWLzrqZu2eO+bwRXIbZot KVJJpVCdEbPUmWsn1o4rKa9YrW+iI1CpxelBnZn+NrwI1Hb29CNYOsrwsluai8EBgwtQ Kr+mtUa2o5XJto+6MphdtGth1N2rzIpe9g7x9Uomo4SqYukeCTqy/I7NbUWySzc2T8mC fDag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:content-language :references:to:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=LwX2JkY0ze5qoxHE8yDK81QnuEc0DDCbSRUUumQxNTo=; b=8M3WBAG+ThXfgQ/KS8hHGyq0AHH5OWlY3s126VyqHDotUvsbhVy6dYoFv1UtHjiPZJ pp2Gk1+KQupWUySkrH2yn3o25YZPc+qfWeBUH9Q7kOzCTUD6G/bb9c69IkZ2Q2BDOl5Y 0TvqRs/5NnIpPPXCxDTo9Qh08EgsBPDoxp+gWS2JWMbu8CFIj1UGJw7WISUv5VMvSacB FvrBFafm9TS7RGjtRXND3C387aHikS1rxztpkM/lHYoJwETqmFgiARVZD1K4hP3Hhok0 mORi3SljqiCcoiTJSZvDth//NuLdbHzRfKGCWF3QwCZODFGfRnrWSz43rJqW6t/0D/js 6vow== X-Gm-Message-State: ANoB5pmGn/vp2cydNdgNZwErQa08+He21cw5rUOgV83h91siib+swmdh 8ocj9n9d198vh790uMVrUT36WA== X-Google-Smtp-Source: AA0mqf7w4VZlmq7FhIbsQhjE/zcZqb9HdNk+tGu+KlapivLb7CKc7DgqYUrH8aiWZiF8Ufd01wJnhQ== X-Received: by 2002:ac2:58cd:0:b0:4b5:7d38:a636 with SMTP id u13-20020ac258cd000000b004b57d38a636mr850205lfo.109.1670258628121; Mon, 05 Dec 2022 08:43:48 -0800 (PST) Received: from [192.168.1.211] ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id q18-20020a056512211200b004ae394b6a6fsm2173265lfr.246.2022.12.05.08.43.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 05 Dec 2022 08:43:47 -0800 (PST) Message-ID: Date: Mon, 5 Dec 2022 18:43:46 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.5.0 Subject: Re: [PATCH v3 09/11] arm64: dts: qcom: sm8350: Add display system nodes To: Robert Foss , robdclark@gmail.com, quic_abhinavk@quicinc.com, sean@poorly.run, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, konrad.dybcio@somainline.org, quic_kalyant@quicinc.com, angelogioacchino.delregno@somainline.org, loic.poulain@linaro.org, swboyd@chromium.org, quic_vpolimer@quicinc.com, vkoul@kernel.org, dianders@chromium.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Marek , vinod.koul@linaro.org, quic_jesszhan@quicinc.com, andersson@kernel.org References: <20221205163754.221139-1-robert.foss@linaro.org> <20221205163754.221139-10-robert.foss@linaro.org> Content-Language: en-GB From: Dmitry Baryshkov In-Reply-To: <20221205163754.221139-10-robert.foss@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 05/12/2022 18:37, Robert Foss wrote: > Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these > nodes the display subsystem is configured to support > one DSI output. > > Signed-off-by: Robert Foss > --- > arch/arm64/boot/dts/qcom/sm8350.dtsi | 199 ++++++++++++++++++++++++++- > 1 file changed, 195 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi > index 434f8e8b12c1..fb1c616c5e89 100644 > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi > @@ -3,6 +3,7 @@ > * Copyright (c) 2020, Linaro Limited > */ > > +#include > #include > #include > #include > @@ -2536,14 +2537,203 @@ usb_2_dwc3: usb@a800000 { > }; > }; > > + mdss: mdss@ae00000 { display-sybsystem@ I also had this issue in sm8450.dtsi (and I'm going to fix it in the next revision). > + compatible = "qcom,sm8350-mdss"; > + reg = <0 0x0ae00000 0 0x1000>; > + reg-names = "mdss"; > + > + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, > + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; > + interconnect-names = "mdp0-mem", "mdp1-mem"; > + > + power-domains = <&dispcc MDSS_GDSC>; > + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>, > + <&gcc GCC_DISP_SF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>; > + clock-names = "iface", "bus", "nrt_bus", "core"; > + > + interrupts = ; > + interrupt-controller; > + #interrupt-cells = <1>; > + > + iommus = <&apps_smmu 0x820 0x402>; > + > + status = "disabled"; > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + mdss_mdp: display-controller@ae01000 { > + compatible = "qcom,sm8350-dpu"; > + reg = <0 0x0ae01000 0 0x8f000>, > + <0 0x0aeb0000 0 0x2008>; > + reg-names = "mdp", "vbif"; > + > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, > + <&gcc GCC_DISP_SF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>, > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + clock-names = "bus", > + "nrt_bus", > + "iface", > + "lut", > + "core", > + "vsync"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + assigned-clock-rates = <19200000>; > + > + operating-points-v2 = <&mdp_opp_table>; > + power-domains = <&rpmhpd SM8350_MMCX>; > + > + interrupt-parent = <&mdss>; > + interrupts = <0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dpu_intf1_out: endpoint { > + remote-endpoint = <&dsi0_in>; > + }; > + }; > + }; > + }; > + > + dsi0: dsi@ae94000 { > + compatible = "qcom,mdss-dsi-ctrl"; > + reg = <0 0x0ae94000 0 0x400>; > + reg-names = "dsi_ctrl"; > + > + interrupt-parent = <&mdss>; > + interrupts = <4>; > + > + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, > + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, > + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, > + <&dispcc DISP_CC_MDSS_ESC0_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>; > + clock-names = "byte", > + "byte_intf", > + "pixel", > + "core", > + "iface", > + "bus"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, > + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; > + assigned-clock-parents = <&dsi0_phy 0>, > + <&dsi0_phy 1>; > + > + operating-points-v2 = <&dsi_opp_table>; > + power-domains = <&rpmhpd SM8350_MMCX>; > + > + phys = <&dsi0_phy>; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dsi0_in: endpoint { > + remote-endpoint = <&dpu_intf1_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + dsi0_out: endpoint { > + }; > + }; > + }; > + > + mdp_opp_table: opp-table { The mdp (dpu?) opp table belongs to the display-controller node. > + compatible = "operating-points-v2"; > + > + /* TODO: opp-200000000 should work with > + * &rpmhpd_opp_low_svs, but one some of > + * sm8350_hdk boards reboot using this > + * opp. > + */ > + opp-200000000 { > + opp-hz = /bits/ 64 <200000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + I have been changing the dsi's opp table, not this one. > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-345000000 { > + opp-hz = /bits/ 64 <345000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-460000000 { > + opp-hz = /bits/ 64 <460000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + }; > + > + dsi0_phy: phy@ae94400 { > + compatible = "qcom,dsi-phy-5nm-8350"; > + reg = <0 0x0ae94400 0 0x200>, > + <0 0x0ae94600 0 0x280>, > + <0 0x0ae94900 0 0x260>; > + reg-names = "dsi_phy", > + "dsi_phy_lane", > + "dsi_pll"; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "iface", "ref"; > + > + status = "disabled"; > + > + dsi_opp_table: dsi-opp-table { And this table should go to dsi node. > + compatible = "operating-points-v2"; > + > + opp-187500000 { > + opp-hz = /bits/ 64 <187500000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-358000000 { > + opp-hz = /bits/ 64 <358000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + }; > + }; > + }; > + > dispcc: clock-controller@af00000 { > compatible = "qcom,sm8350-dispcc"; > reg = <0 0x0af00000 0 0x10000>; > clocks = <&rpmhcc RPMH_CXO_CLK>, > - <0>, > - <0>, > - <0>, > - <0>, > + <&dsi0_phy 0>, <&dsi0_phy 1>, > + <0>, <0>, Let's probably add both DSI controllers and DSI PHYs. It's fine if you can not verify the second one for real. > <0>, > <0>; > clock-names = "bi_tcxo", > @@ -2558,6 +2748,7 @@ dispcc: clock-controller@af00000 { > #power-domain-cells = <1>; > > power-domains = <&rpmhpd SM8350_MMCX>; > + required-opps = <&rpmhpd_opp_low_svs>; As it's not a turbo level anymore, can we drop it completely? > }; > > adsp: remoteproc@17300000 { -- With best wishes Dmitry