From: Wesley Cheng <wcheng@codeaurora.org>
To: Manu Gautam <mgautam@codeaurora.org>,
agross@kernel.org, bjorn.andersson@linaro.org, kishon@ti.com,
robh+dt@kernel.org, mark.rutland@arm.com, p.zabel@pengutronix.de
Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH v4 4/4] phy: qcom-qmp: Use proper PWRDOWN offset for sm8150 USB
Date: Thu, 2 Apr 2020 11:31:40 -0700 [thread overview]
Message-ID: <b70f88cd-bbc7-96ab-3890-e15cbe94b258@codeaurora.org> (raw)
In-Reply-To: <d61723e3-17a3-366d-f476-c33931766efd@codeaurora.org>
Hi Manu,
Thanks for the feedback and review.
On 4/2/2020 12:35 AM, Manu Gautam wrote:
>
> On 3/31/2020 1:06 AM, Wesley Cheng wrote:
>> The register map for SM8150 QMP USB SSPHY has moved
>> QPHY_POWER_DOWN_CONTROL to a different offset. Allow for
>> an offset in the register table to override default value
>> if it is a DP capable PHY.
>>
>> Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
>> ---
>> drivers/phy/qualcomm/phy-qcom-qmp.c | 15 ++++++++++++---
>> 1 file changed, 12 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
>> index cc04471..4c0517e 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qmp.c
>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
>> @@ -164,6 +164,7 @@ enum qphy_reg_layout {
>> [QPHY_SW_RESET] = 0x00,
>> [QPHY_START_CTRL] = 0x44,
>> [QPHY_PCS_STATUS] = 0x14,
>> + [QPHY_COM_POWER_DOWN_CONTROL] = 0x40,
> Since this is in PCS block please rename it to -
>
> QPHY_PCS_POWER_DOWN_CONTROL
>
Sure, will add another enum value to the register layout, and rename it
where needed.
>> };
>>
>> static const unsigned int sdm845_ufsphy_regs_layout[] = {
>> @@ -1627,6 +1628,9 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
>> if (cfg->has_phy_com_ctrl)
>> qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
>> SW_PWRDN);
>> + else if (cfg->has_phy_dp_com_ctrl && cfg->regs[QPHY_COM_POWER_DOWN_CONTROL])
>> + qphy_setbits(pcs, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
>> + cfg->pwrdn_ctrl);
>> else
>> qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
> Since, this register is in PCS block why check for dp_com_ctrl here?
> Something like:
>
> if (cfg->has_phy_com_ctrl) {
> qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
> SW_PWRDN);
> } else {
> if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
> qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
> cfg->pwrdn_ctrl);
> else
> qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
> }
>
Agree with this.
>>
>> @@ -1671,10 +1675,12 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
>> return ret;
>> }
>>
>> -static int qcom_qmp_phy_com_exit(struct qcom_qmp *qmp)
>> +static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
>> {
>> + struct qcom_qmp *qmp = qphy->qmp;
>> const struct qmp_phy_cfg *cfg = qmp->cfg;
>> void __iomem *serdes = qmp->serdes;
>> + void __iomem *pcs = qphy->pcs;
>> int i = cfg->num_resets;
>>
>> mutex_lock(&qmp->phy_mutex);
>> @@ -1691,6 +1697,9 @@ static int qcom_qmp_phy_com_exit(struct qcom_qmp *qmp)
>> SW_RESET);
>> qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
>> SW_PWRDN);
>> + } else if (cfg->has_phy_dp_com_ctrl && cfg->regs[QPHY_COM_POWER_DOWN_CONTROL]) {
>
> Can we add change similar to init() here ?
>
>
Sure. I will move this check to where the current code writes to the
PWR DOWN CONTROL in
static int qcom_qmp_phy_disable(struct phy *phy)
{
...
qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
We wouldn't want the SW to write to an incorrect register.
>> + cfg->pwrdn_ctrl);
>> }
>>
>> while (--i >= 0)
>> @@ -1829,7 +1838,7 @@ static int qcom_qmp_phy_enable(struct phy *phy)
>> if (cfg->has_lane_rst)
>> reset_control_assert(qphy->lane_rst);
>> err_lane_rst:
>> - qcom_qmp_phy_com_exit(qmp);
>> + qcom_qmp_phy_com_exit(qphy);
>>
>> return ret;
>> }
>> @@ -1855,7 +1864,7 @@ static int qcom_qmp_phy_disable(struct phy *phy)
>> if (cfg->has_lane_rst)
>> reset_control_assert(qphy->lane_rst);
>>
>> - qcom_qmp_phy_com_exit(qmp);
>> + qcom_qmp_phy_com_exit(qphy);
>>
>> qmp->phy_initialized = false;
>>
>
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
prev parent reply other threads:[~2020-04-02 18:32 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-30 19:36 [PATCH v4 0/4] Add SS/HS-USB changes for Qualcomm SM8150 chipset Wesley Cheng
2020-03-30 19:36 ` [PATCH v4 1/4] dt-bindings: phy: Add binding for qcom,usb-hs-7nm Wesley Cheng
2020-03-30 19:36 ` [PATCH v4 2/4] phy: qcom-snps: Add SNPS USB PHY driver for QCOM based SOCs Wesley Cheng
2020-04-02 6:43 ` Manu Gautam
2020-04-03 0:32 ` Wesley Cheng
2020-03-30 19:36 ` [PATCH v4 3/4] phy: qcom-qmp: Add SM8150 QMP USB3 PHY support Wesley Cheng
2020-04-02 7:00 ` Manu Gautam
2020-04-02 23:06 ` Wesley Cheng
2020-03-30 19:36 ` [PATCH v4 4/4] phy: qcom-qmp: Use proper PWRDOWN offset for sm8150 USB Wesley Cheng
2020-04-02 7:35 ` Manu Gautam
2020-04-02 18:31 ` Wesley Cheng [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=b70f88cd-bbc7-96ab-3890-e15cbe94b258@codeaurora.org \
--to=wcheng@codeaurora.org \
--cc=agross@kernel.org \
--cc=bjorn.andersson@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=kishon@ti.com \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=mgautam@codeaurora.org \
--cc=p.zabel@pengutronix.de \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).