From: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
To: Depeng Shao <quic_depengs@quicinc.com>,
rfoss@kernel.org, todor.too@gmail.com,
bryan.odonoghue@linaro.org, mchehab@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org
Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
kernel@quicinc.com, Yongsheng Li <quic_yon@quicinc.com>
Subject: Re: [PATCH 13/13] media: qcom: camss: Add support for VFE hardware version Titan 780
Date: Wed, 14 Aug 2024 17:23:40 +0100 [thread overview]
Message-ID: <b78f23ca-eb6e-45cf-9e42-86c906ff901f@linaro.org> (raw)
In-Reply-To: <20240812144131.369378-14-quic_depengs@quicinc.com>
On 12/08/2024 15:41, Depeng Shao wrote:
> Add support for VFE found on SM8550 (Titan 780). This implementation is
> based on the titan 480 implementation. It supports the normal and lite
> VFE.
>
> Co-developed-by: Yongsheng Li <quic_yon@quicinc.com>
> Signed-off-by: Yongsheng Li <quic_yon@quicinc.com>
> Signed-off-by: Depeng Shao <quic_depengs@quicinc.com>
> ---
> drivers/media/platform/qcom/camss/Makefile | 1 +
> .../media/platform/qcom/camss/camss-vfe-780.c | 148 ++++++++++++++++++
> drivers/media/platform/qcom/camss/camss-vfe.c | 33 ++--
> drivers/media/platform/qcom/camss/camss-vfe.h | 1 +
> drivers/media/platform/qcom/camss/camss.c | 132 ++++++++++++++++
> drivers/media/platform/qcom/camss/camss.h | 2 +
> 6 files changed, 304 insertions(+), 13 deletions(-)
> create mode 100644 drivers/media/platform/qcom/camss/camss-vfe-780.c
>
> diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile
> index c336e4c1a399..a83b7a8dcef7 100644
> --- a/drivers/media/platform/qcom/camss/Makefile
> +++ b/drivers/media/platform/qcom/camss/Makefile
> @@ -17,6 +17,7 @@ qcom-camss-objs += \
> camss-vfe-4-8.o \
> camss-vfe-17x.o \
> camss-vfe-480.o \
> + camss-vfe-780.o \
> camss-vfe-gen1.o \
> camss-vfe.o \
> camss-video.o \
> diff --git a/drivers/media/platform/qcom/camss/camss-vfe-780.c b/drivers/media/platform/qcom/camss/camss-vfe-780.c
> new file mode 100644
> index 000000000000..e1c4d25cdc40
> --- /dev/null
> +++ b/drivers/media/platform/qcom/camss/camss-vfe-780.c
> @@ -0,0 +1,148 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * camss-vfe-780.c
> + *
> + * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v780 (SM8550)
> + *
> + * Copyright (c) 2024 Qualcomm Technologies, Inc.
> + */
> +
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +
> +#include "camss.h"
> +#include "camss-vfe.h"
> +
> +#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x200 : 0xC00)
> +
> +#define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08)
> +#define WM_CGC_OVERRIDE_ALL (0x7FFFFFF)
> +
> +#define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0xDC)
> +
> +#define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x200 + (n) * 0x100)
> +#define WM_CFG_EN BIT(0)
> +#define WM_VIR_FRM_EN BIT(1)
> +#define WM_CFG_MODE BIT(16)
> +#define VFE_BUS_WM_IMAGE_ADDR(n) (BUS_REG_BASE + 0x204 + (n) * 0x100)
> +#define VFE_BUS_WM_FRAME_INCR(n) (BUS_REG_BASE + 0x208 + (n) * 0x100)
> +#define VFE_BUS_WM_IMAGE_CFG_0(n) (BUS_REG_BASE + 0x20c + (n) * 0x100)
> +#define WM_IMAGE_CFG_0_DEFAULT_WIDTH (0xFFFF)
> +#define VFE_BUS_WM_IMAGE_CFG_1(n) (BUS_REG_BASE + 0x210 + (n) * 0x100)
> +#define VFE_BUS_WM_IMAGE_CFG_2(n) (BUS_REG_BASE + 0x214 + (n) * 0x100)
> +#define WM_IMAGE_CFG_2_DEFAULT_STRIDE (0xFFFF)
> +#define VFE_BUS_WM_PACKER_CFG(n) (BUS_REG_BASE + 0x218 + (n) * 0x100)
> +#define VFE_BUS_WM_HEADER_ADDR(n) (BUS_REG_BASE + 0x220 + (n) * 0x100)
> +#define VFE_BUS_WM_HEADER_INCR(n) (BUS_REG_BASE + 0x224 + (n) * 0x100)
> +#define VFE_BUS_WM_HEADER_CFG(n) (BUS_REG_BASE + 0x228 + (n) * 0x100)
> +
> +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) (BUS_REG_BASE + 0x230 + (n) * 0x100)
> +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n) (BUS_REG_BASE + 0x234 + (n) * 0x100)
> +#define VFE_BUS_WM_FRAMEDROP_PERIOD(n) (BUS_REG_BASE + 0x238 + (n) * 0x100)
> +#define VFE_BUS_WM_FRAMEDROP_PATTERN(n) (BUS_REG_BASE + 0x23c + (n) * 0x100)
> +
> +#define VFE_BUS_WM_MMU_PREFETCH_CFG(n) (BUS_REG_BASE + 0x260 + (n) * 0x100)
> +#define VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(n) (BUS_REG_BASE + 0x264 + (n) * 0x100)
> +#define VFE_BUS_WM_SYSTEM_CACHE_CFG(n) (BUS_REG_BASE + 0x268 + (n) * 0x100)
> +
> +/* for titan 780, each bus client is hardcoded to a specific path */
> +#define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x17) + (n))
> +
> +static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line)
> +{
> + struct v4l2_pix_format_mplane *pix =
> + &line->video_out.active_fmt.fmt.pix_mp;
> +
> + wm = RDI_WM(wm); /* map to actual WM used (from wm=RDI index) */
> +
> + /* no clock gating at bus input */
> + writel(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE);
> +
> + writel(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL);
> +
> + writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height >> 8,
> + vfe->base + VFE_BUS_WM_FRAME_INCR(wm));
> + writel((WM_IMAGE_CFG_0_DEFAULT_WIDTH & 0xFFFF),
> + vfe->base + VFE_BUS_WM_IMAGE_CFG_0(wm));
> + writel(WM_IMAGE_CFG_2_DEFAULT_STRIDE,
> + vfe->base + VFE_BUS_WM_IMAGE_CFG_2(wm));
> + writel(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm));
> +
> + /* no dropped frames, one irq per frame */
> + writel(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm));
> + writel(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm));
> + writel(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm));
> + writel(1, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(wm));
> +
> + writel(1, vfe->base + VFE_BUS_WM_MMU_PREFETCH_CFG(wm));
> + writel(0xFFFFFFFF, vfe->base + VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(wm));
> +
> + writel(WM_CFG_EN | WM_CFG_MODE, vfe->base + VFE_BUS_WM_CFG(wm));
> +}
> +
> +static void vfe_wm_stop(struct vfe_device *vfe, u8 wm)
> +{
> + wm = RDI_WM(wm); /* map to actual WM used (from wm=RDI index) */
> + writel(0, vfe->base + VFE_BUS_WM_CFG(wm));
> +}
> +
> +static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr,
> + struct vfe_line *line)
> +{
> + wm = RDI_WM(wm); /* map to actual WM used (from wm=RDI index) */
> + writel((addr >> 8) & 0xFFFFFFFF, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm));
> +
> + dev_dbg(vfe->camss->dev, "%s wm:%d, image buf addr:0x%x\n",
> + __func__, wm, addr);
> +}
> +
> +static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id)
> +{
> + int port_id = line_id;
> +
> + /* RUP(register update) registers has beem moved to CSID in Titan 780.
> + * Notify the event of trigger RUP.
> + */
> + camss_reg_update(vfe->camss, vfe->id, port_id, false);
> +}
> +
> +static inline void vfe_reg_update_clear(struct vfe_device *vfe,
> + enum vfe_line_id line_id)
> +{
> + int port_id = line_id;
> +
> + /* RUP(register update) registers has beem moved to CSID in Titan 780.
> + * Notify the event of trigger RUP clear.
> + */
> + camss_reg_update(vfe->camss, vfe->id, port_id, true);
> +}
> +
> +static const struct camss_video_ops vfe_video_ops_780 = {
> + .queue_buffer = vfe_queue_buffer_v2,
> + .flush_buffers = vfe_flush_buffers,
> +};
> +
> +static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe)
> +{
> + vfe->video_ops = vfe_video_ops_780;
> +}
> +
> +const struct vfe_hw_ops vfe_ops_780 = {
> + .enable_irq = NULL,
> + .global_reset = NULL,
> + .hw_version = vfe_hw_version,
> + .isr = NULL,
> + .pm_domain_off = vfe_pm_domain_off,
> + .pm_domain_on = vfe_pm_domain_on,
> + .subdev_init = vfe_subdev_init,
> + .vfe_disable = vfe_disable,
> + .vfe_enable = vfe_enable_v2,
> + .vfe_halt = NULL,
> + .vfe_wm_start = vfe_wm_start,
> + .vfe_wm_stop = vfe_wm_stop,
> + .vfe_buf_done = vfe_buf_done,
> + .vfe_wm_update = vfe_wm_update,
> + .reg_update = vfe_reg_update,
> + .reg_update_clear = vfe_reg_update_clear,
> +};
> diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
> index 71bd55e854bb..507fc7785ac8 100644
> --- a/drivers/media/platform/qcom/camss/camss-vfe.c
> +++ b/drivers/media/platform/qcom/camss/camss-vfe.c
> @@ -343,6 +343,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
> case CAMSS_845:
> case CAMSS_8250:
> case CAMSS_8280XP:
> + case CAMSS_8550:
> switch (sink_code) {
> case MEDIA_BUS_FMT_YUYV8_1X16:
> {
> @@ -674,15 +675,17 @@ int vfe_reset(struct vfe_device *vfe)
> {
> unsigned long time;
>
> - reinit_completion(&vfe->reset_complete);
> + if (vfe->res->hw_ops->global_reset) {
> + reinit_completion(&vfe->reset_complete);
>
> - vfe->res->hw_ops->global_reset(vfe);
> + vfe->res->hw_ops->global_reset(vfe);
>
> - time = wait_for_completion_timeout(&vfe->reset_complete,
> - msecs_to_jiffies(VFE_RESET_TIMEOUT_MS));
> - if (!time) {
> - dev_err(vfe->camss->dev, "VFE reset timeout\n");
> - return -EIO;
> + time = wait_for_completion_timeout(&vfe->reset_complete,
> + msecs_to_jiffies(VFE_RESET_TIMEOUT_MS));
> + if (!time) {
> + dev_err(vfe->camss->dev, "VFE reset timeout\n");
> + return -EIO;
> + }
Per my comment on the CSID - this feels like a fix you are introducing
here in the guise of a silicon add.
Please break it up.
If you have a number of fixes to core functionality they need to be
1. Granular and individual
2. Indivdually scrutable with their own patch and descritption
3. git cherry-pickable
4. Have a Fixes tag
5. And be cc'd to stable@vger.kernel.org
Can't accept either the fixes or the silicon add if the two live mixed
up in one patch.
> }
>
> return 0;
> @@ -1120,7 +1123,8 @@ void vfe_put(struct vfe_device *vfe)
> } else if (vfe->power_count == 1) {
> if (vfe->was_streaming) {
> vfe->was_streaming = 0;
> - vfe->res->hw_ops->vfe_halt(vfe);
> + if (vfe->res->hw_ops->vfe_halt)
> + vfe->res->hw_ops->vfe_halt(vfe);
Similar comment.
> }
> camss_disable_clocks(vfe->nclocks, vfe->clock);
> pm_runtime_put_sync(vfe->camss->dev);
> @@ -1807,11 +1811,13 @@ int msm_vfe_subdev_init(struct camss *camss, struct vfe_device *vfe,
> vfe->irq = ret;
> snprintf(vfe->irq_name, sizeof(vfe->irq_name), "%s_%s%d",
> dev_name(dev), MSM_VFE_NAME, id);
> - ret = devm_request_irq(dev, vfe->irq, vfe->res->hw_ops->isr,
> - IRQF_TRIGGER_RISING, vfe->irq_name, vfe);
> - if (ret < 0) {
> - dev_err(dev, "request_irq failed: %d\n", ret);
> - return ret;
> + if (vfe->res->hw_ops->isr) {
And again.
> + ret = devm_request_irq(dev, vfe->irq, vfe->res->hw_ops->isr,
> + IRQF_TRIGGER_RISING, vfe->irq_name, vfe);
> + if (ret < 0) {
> + dev_err(dev, "request_irq failed: %d\n", ret);
> + return ret;
> + }
> }
>
> /* Clocks */
> @@ -1963,6 +1969,7 @@ static int vfe_bpl_align(struct vfe_device *vfe)
> case CAMSS_845:
> case CAMSS_8250:
> case CAMSS_8280XP:
> + case CAMSS_8550:
> ret = 16;
> break;
> default:
> diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h b/drivers/media/platform/qcom/camss/camss-vfe.h
> index fcbf4f609129..9dec5bc0d1b1 100644
> --- a/drivers/media/platform/qcom/camss/camss-vfe.h
> +++ b/drivers/media/platform/qcom/camss/camss-vfe.h
> @@ -243,6 +243,7 @@ extern const struct vfe_hw_ops vfe_ops_4_7;
> extern const struct vfe_hw_ops vfe_ops_4_8;
> extern const struct vfe_hw_ops vfe_ops_170;
> extern const struct vfe_hw_ops vfe_ops_480;
> +extern const struct vfe_hw_ops vfe_ops_780;
>
> int vfe_get(struct vfe_device *vfe);
> void vfe_put(struct vfe_device *vfe);
> diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
> index 7ee102948dc4..92a0fa02e415 100644
> --- a/drivers/media/platform/qcom/camss/camss.c
> +++ b/drivers/media/platform/qcom/camss/camss.c
> @@ -1666,6 +1666,125 @@ static const struct camss_subdev_resources csid_res_8550[] = {
> }
> };
>
> +static const struct camss_subdev_resources vfe_res_8550[] = {
> + /* VFE0 */
> + {
> + .regulators = {},
> + .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb_clk", "vfe0_fast_ahb",
> + "vfe0", "cpas_vfe0", "camnoc_axi" },
Should the camnoc AXI clock go here or in the CSID ?
> + .clock_rate = { { 0, 0, 0, 0, 0 },
> + { 0, 0, 0, 0, 80000000 },
> + { 300000000, 300000000, 400000000, 400000000, 400000000 },
> + { 300000000, 300000000, 400000000, 400000000, 400000000 },
> + { 466000000, 594000000, 675000000, 785000000, 785000000 },
> + { 300000000, 300000000, 400000000, 400000000, 400000000 },
> + { 300000000, 300000000, 400000000, 400000000, 400000000 } },
> + .reg = { "vfe0" },
> + .interrupt = { "vfe0" },
> + .vfe = {
> + .line_num = 3,
> + .is_lite = false,
> + .has_pd = true,
> + .pd_name = "ife0",
> + .hw_ops = &vfe_ops_780,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + }
> + },
> + /* VFE1 */
> + {
> + .regulators = {},
> + .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb_clk", "vfe1_fast_ahb",
> + "vfe1", "cpas_vfe1", "camnoc_axi" },
> + .clock_rate = { { 0, 0, 0, 0, 0 },
> + { 0, 0, 0, 0, 80000000 },
> + { 300000000, 300000000, 400000000, 400000000, 400000000 },
> + { 300000000, 300000000, 400000000, 400000000, 400000000 },
> + { 466000000, 594000000, 675000000, 785000000, 785000000 },
> + { 300000000, 300000000, 400000000, 400000000, 400000000 },
> + { 300000000, 300000000, 400000000, 400000000, 400000000 } },
> + .reg = { "vfe1" },
> + .interrupt = { "vfe1" },
> + .vfe = {
> + .line_num = 3,
> + .is_lite = false,
> + .has_pd = true,
> + .pd_name = "ife1",
> + .hw_ops = &vfe_ops_780,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + }
> + },
> + /* VFE2 */
> + {
> + .regulators = {},
> + .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb_clk", "vfe2_fast_ahb",
> + "vfe2", "cpas_vfe2", "camnoc_axi" },
> + .clock_rate = { { 0, 0, 0, 0, 0 },
> + { 0, 0, 0, 0, 80000000 },
> + { 300000000, 300000000, 400000000, 400000000, 400000000 },
> + { 300000000, 300000000, 400000000, 400000000, 400000000 },
> + { 466000000, 594000000, 675000000, 785000000, 785000000 },
> + { 300000000, 300000000, 400000000, 400000000, 400000000 },
> + { 300000000, 300000000, 400000000, 400000000, 400000000 } },
> + .reg = { "vfe2" },
> + .interrupt = { "vfe2" },
> + .vfe = {
> + .line_num = 3,
> + .is_lite = false,
> + .has_pd = true,
> + .pd_name = "ife2",
> + .hw_ops = &vfe_ops_780,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + }
> + },
> + /* VFE3 lite */
> + {
> + .regulators = {},
> + .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb_clk", "vfe_lite_ahb",
> + "vfe_lite", "cpas_ife_lite", "camnoc_axi" },
> + .clock_rate = { { 0, 0, 0, 0, 0 },
> + { 0, 0, 0, 0, 80000000 },
> + { 300000000, 300000000, 400000000, 400000000, 400000000 },
> + { 300000000, 300000000, 400000000, 400000000, 400000000 },
> + { 400000000, 480000000, 480000000, 480000000, 480000000 },
> + { 300000000, 300000000, 400000000, 400000000, 400000000 },
> + { 300000000, 300000000, 400000000, 400000000, 400000000 } },
> + .reg = { "vfe_lite0" },
> + .interrupt = { "vfe_lite0" },
> + .vfe = {
> + .line_num = 4,
> + .is_lite = true,
> + .hw_ops = &vfe_ops_780,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + }
> + },
> + /* VFE4 lite */
> + {
> + .regulators = {},
> + .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb_clk", "vfe_lite_ahb",
> + "vfe_lite", "cpas_ife_lite", "camnoc_axi" },
> + .clock_rate = { { 0, 0, 0, 0, 0 },
> + { 0, 0, 0, 0, 80000000 },
> + { 300000000, 300000000, 400000000, 400000000, 400000000 },
> + { 300000000, 300000000, 400000000, 400000000, 400000000 },
I realise you're specifying all of the operating points here but the
clock only needs to appear once i.e.
1 x 300 MHz
1 x 400 MHz
1 x 480 MHz
etc.
> + { 400000000, 480000000, 480000000, 480000000, 480000000 },
> + { 300000000, 300000000, 400000000, 400000000, 400000000 },
> + { 300000000, 300000000, 400000000, 400000000, 400000000 } },
> + .reg = { "vfe_lite1" },
> + .interrupt = { "vfe_lite1" },
> + .vfe = {
> + .line_num = 4,
> + .is_lite = true,
> + .hw_ops = &vfe_ops_780,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + }
> + },
> +};
> +
> static const struct resources_icc icc_res_sm8550[] = {
> {
> .name = "ahb",
> @@ -1846,6 +1965,17 @@ void camss_pm_domain_off(struct camss *camss, int id)
> }
> }
>
> +void camss_reg_update(struct camss *camss, int hw_id, int port_id, bool is_clear)
> +{
> + struct csid_device *csid;
> +
> + if (hw_id < camss->res->csid_num) {
Does this cause do anything ? Is it just defensive programming ? Can the
hw_id index exceed the number of CSIDs defined and if so why ?
Smells wrong.
> + csid = &(camss->csid[hw_id]);
> +
> + csid->res->hw_ops->reg_update(csid, port_id, is_clear);
> + }
> +}
> +
> void camss_buf_done(struct camss *camss, int hw_id, int port_id)
> {
> struct vfe_device *vfe;
> @@ -2668,10 +2798,12 @@ static const struct camss_resources sm8550_resources = {
> .pd_name = "top",
> .csiphy_res = csiphy_res_8550,
> .csid_res = csid_res_8550,
> + .vfe_res = vfe_res_8550,
> .icc_res = icc_res_sm8550,
> .icc_path_num = ARRAY_SIZE(icc_res_sm8550),
> .csiphy_num = ARRAY_SIZE(csiphy_res_8550),
> .csid_num = ARRAY_SIZE(csid_res_8550),
> + .vfe_num = ARRAY_SIZE(vfe_res_8550),
> .link_entities = camss_link_entities
> };
>
> diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
> index d6b6558a82b9..697846e70e78 100644
> --- a/drivers/media/platform/qcom/camss/camss.h
> +++ b/drivers/media/platform/qcom/camss/camss.h
> @@ -157,5 +157,7 @@ int camss_vfe_get(struct camss *camss, int id);
> void camss_vfe_put(struct camss *camss, int id);
> void camss_delete(struct camss *camss);
> void camss_buf_done(struct camss *camss, int hw_id, int port_id);
> +void camss_reg_update(struct camss *camss, int hw_id,
> + int port_id, bool is_clear);
>
> #endif /* QC_MSM_CAMSS_H */
All in all good work, looks like good progress and thanks for sticking
with your submissions.
Please follow up on the points raised.
---
bod
next prev parent reply other threads:[~2024-08-14 16:23 UTC|newest]
Thread overview: 99+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-12 14:41 [PATCH v4 00/13] media: qcom: camss: Add sm8550 support Depeng Shao
2024-08-12 14:41 ` [PATCH 01/13] media: qcom: camss: csiphy-3ph: Fix trivial indentation fault in defines Depeng Shao
2024-08-12 14:41 ` [PATCH 02/13] media: qcom: camss: csiphy-3ph: Remove redundant PHY init sequence control loop Depeng Shao
2024-08-12 14:41 ` [PATCH 03/13] media: qcom: camss: csiphy-3ph: Rename struct Depeng Shao
2024-08-12 14:41 ` [PATCH 04/13] media: qcom: camss: csiphy: Add an init callback to CSI PHY devices Depeng Shao
2024-08-19 0:17 ` Vladimir Zapolskiy
2024-09-04 14:20 ` Depeng Shao
2024-09-04 14:51 ` Bryan O'Donoghue
2024-08-12 14:41 ` [PATCH 05/13] media: qcom: camss: csiphy-3ph: Move CSIPHY variables to data field inside csiphy struct Depeng Shao
2024-08-19 0:01 ` Vladimir Zapolskiy
2024-08-28 14:11 ` Depeng Shao
2024-08-12 14:41 ` [PATCH 06/13] media: qcom: camss: csiphy-3ph: Use an offset variable to find common control regs Depeng Shao
2024-08-18 23:59 ` Vladimir Zapolskiy
2024-08-12 14:41 ` [PATCH 07/13] dt-bindings: media: camss: Add qcom,sm8550-camss binding Depeng Shao
2024-08-16 7:01 ` Krzysztof Kozlowski
2024-08-16 7:45 ` Depeng Shao
2024-09-30 7:17 ` Krzysztof Kozlowski
2024-09-05 15:20 ` Vladimir Zapolskiy
2024-09-05 15:54 ` Depeng Shao
2024-09-06 15:56 ` Vladimir Zapolskiy
2024-09-25 15:13 ` Depeng Shao
2024-09-30 7:16 ` Krzysztof Kozlowski
2024-09-30 8:46 ` Vladimir Zapolskiy
2024-09-30 8:55 ` Bryan O'Donoghue
2024-09-30 9:15 ` Vladimir Zapolskiy
2024-09-30 7:26 ` Krzysztof Kozlowski
2024-09-30 8:32 ` Vladimir Zapolskiy
2024-09-30 9:03 ` Bryan O'Donoghue
2024-09-12 8:22 ` Vladimir Zapolskiy
2024-09-12 11:41 ` Bryan O'Donoghue
2024-09-12 12:44 ` Vladimir Zapolskiy
2024-09-12 15:11 ` Bryan O'Donoghue
2024-09-12 20:57 ` Vladimir Zapolskiy
2024-09-12 22:41 ` Bryan O'Donoghue
2024-09-13 5:06 ` Vladimir Zapolskiy
2024-09-17 22:40 ` Bryan O'Donoghue
2024-09-17 23:16 ` Vladimir Zapolskiy
2024-09-25 15:40 ` Depeng Shao
2024-09-30 9:26 ` Depeng Shao
2024-10-08 13:50 ` Vladimir Zapolskiy
2024-10-08 14:06 ` Bryan O'Donoghue
2024-10-08 15:47 ` Depeng Shao
2024-09-30 10:21 ` Bryan O'Donoghue
2024-09-13 4:17 ` Dmitry Baryshkov
2024-09-12 13:48 ` Neil Armstrong
2024-08-12 14:41 ` [PATCH 08/13] media: qcom: camss: csid: Move common code into csid core Depeng Shao
2024-08-14 23:53 ` Bryan O'Donoghue
2024-08-24 12:50 ` Vladimir Zapolskiy
2024-08-12 14:41 ` [PATCH 09/13] media: qcom: camss: vfe: Move common code into vfe core Depeng Shao
2024-08-15 0:09 ` Bryan O'Donoghue
2024-08-16 13:07 ` Depeng Shao
2024-08-24 13:06 ` Vladimir Zapolskiy
2024-08-28 0:07 ` Bryan O'Donoghue
2024-09-02 13:11 ` Depeng Shao
2024-08-12 14:41 ` [PATCH 10/13] media: qcom: camss: Add sm8550 compatible Depeng Shao
2024-08-13 12:57 ` Bryan O'Donoghue
2024-08-12 14:41 ` [PATCH 11/13] media: qcom: camss: csiphy-3ph: Add Gen2 v2.1.2 two-phase MIPI CSI-2 DPHY support Depeng Shao
2024-08-12 14:41 ` [PATCH 12/13] media: qcom: camss: Add CSID Gen3 support for sm8550 Depeng Shao
2024-08-14 16:08 ` Bryan O'Donoghue
2024-08-15 15:14 ` Depeng Shao
2024-08-15 16:10 ` Bryan O'Donoghue
2024-08-16 11:34 ` Bryan O'Donoghue
2024-08-16 13:11 ` Depeng Shao
2024-08-16 14:21 ` Bryan O'Donoghue
2024-08-19 13:23 ` Depeng Shao
2024-08-16 14:45 ` Bryan O'Donoghue
2024-08-19 13:18 ` Depeng Shao
2024-08-16 14:49 ` Bryan O'Donoghue
2024-08-24 13:19 ` Vladimir Zapolskiy
2024-09-30 9:23 ` Vladimir Zapolskiy
2024-09-30 9:38 ` Depeng Shao
2024-08-12 14:41 ` [PATCH 13/13] media: qcom: camss: Add support for VFE hardware version Titan 780 Depeng Shao
2024-08-14 11:13 ` Vladimir Zapolskiy
2024-08-14 13:10 ` Depeng Shao
2024-08-14 23:20 ` Vladimir Zapolskiy
2024-08-15 14:42 ` Depeng Shao
2024-08-15 14:57 ` Vladimir Zapolskiy
2024-08-15 15:43 ` Depeng Shao
2024-08-15 21:31 ` Vladimir Zapolskiy
2024-08-16 12:42 ` Depeng Shao
2024-08-20 14:01 ` Vladimir Zapolskiy
2024-08-14 16:23 ` Bryan O'Donoghue [this message]
2024-08-15 13:33 ` Depeng Shao
2024-08-15 16:16 ` Bryan O'Donoghue
2024-08-15 0:16 ` Bryan O'Donoghue
2024-08-15 14:24 ` Depeng Shao
2024-08-15 0:25 ` Bryan O'Donoghue
2024-08-15 14:21 ` Depeng Shao
2024-08-15 16:17 ` Bryan O'Donoghue
2024-09-29 1:28 ` Depeng Shao
2024-09-29 23:57 ` Bryan O'Donoghue
2024-09-30 5:37 ` Depeng Shao
2024-08-19 11:05 ` Bryan O'Donoghue
2024-08-19 13:07 ` Depeng Shao
2024-08-21 11:11 ` Vladimir Zapolskiy
2024-08-24 13:31 ` Vladimir Zapolskiy
2024-08-27 13:16 ` Bryan O'Donoghue
2024-08-13 12:35 ` [PATCH v4 00/13] media: qcom: camss: Add sm8550 support Bryan O'Donoghue
2024-08-13 12:42 ` Depeng Shao
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=b78f23ca-eb6e-45cf-9e42-86c906ff901f@linaro.org \
--to=bryan.odonoghue@linaro.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=kernel@quicinc.com \
--cc=krzk+dt@kernel.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-media@vger.kernel.org \
--cc=mchehab@kernel.org \
--cc=quic_depengs@quicinc.com \
--cc=quic_yon@quicinc.com \
--cc=rfoss@kernel.org \
--cc=robh@kernel.org \
--cc=todor.too@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).