From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 537CB2868B; Fri, 10 Oct 2025 00:33:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760056389; cv=none; b=LCMJXgkXNOVmJkdgBDkobCOkHIRc5NJkZHO44HcnjfB4c0mrfqv3NYBR7xFfV9+lv12sxIc0aDIzp1wD5/HX2j+6GRbBMx8xd2Zo58K2EFXkvuWu63qVJFY0Lck+wsGnqTR0NOgEkvYrO21Y6O5yzCOYnaw+3DHAikgmv04tR0E= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760056389; c=relaxed/simple; bh=xsZLpUTd6ZTK65e7bMtoQS9JRzxyuvAYRVqbj4aTgek=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=t73MKSstEVVeF4jaXeA3/3la0CSi29TRGcQHMOWWmhccltPx3t+t2IYTygo58xV+eV9y73LYVirXm7ysALFJgyQwIK/o4zSJovUiP/Z0GKeXPHadLGWwIMpFQzm2vFOL5ZNzYFOFAw7G5DzTJySbSyKN1xVH2guXQhL6qM96CNg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=c8TSKr/0; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="c8TSKr/0" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 919CCC4CEE7; Fri, 10 Oct 2025 00:33:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1760056388; bh=xsZLpUTd6ZTK65e7bMtoQS9JRzxyuvAYRVqbj4aTgek=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=c8TSKr/0t/FbqVip1LLM9ZPZciprfQ0o2wwRdgt3GGqMcCClwQ6ebY+jCMHLIhGn0 gvOl3s2/JFpLPiDXpqAtz7/qGaflEUx9Ams22/MYw3zMFr0m3IdU65wQV6hfX5BFpw DEdxvdx1IuVR4igsEACUDOAhQiRLyd+WVqMSk8XUtLqwSk8iWwWCif0VoIQx3VFoBZ MgPl8+bnUQxSJPuTNw3qfW4EC26fqG2jhuDFIIVl8eGEFcE2Bzi/BaEkQGIYEB/M3l obqAb3QqiEclT/yAJf6QtIWlZZVToq2Q/yBM3XP2xHvUqeGGsfZw42jngSbAcb634T m2wXpxQLW8fkg== Message-ID: Date: Fri, 10 Oct 2025 02:33:02 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/2] dt-bindings: spmi: add bindings for glymur-spmi-pmic-arb (arbiter v8) To: Kamal Wadhwa , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Jishnu Prakash , David Collins , Pankaj Patil References: <20250924-glymur-spmi-v8-v2-0-202fc7a66a97@oss.qualcomm.com> <20250924-glymur-spmi-v8-v2-1-202fc7a66a97@oss.qualcomm.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 24/09/2025 01:57, Kamal Wadhwa wrote: > From: Jishnu Prakash > > SPMI PMIC Arbiter version 8 builds upon version 7 with support for > up to four SPMI buses. To achieve this, the register map was A nit, subject: drop second/last, redundant "bindings for". The "dt-bindings" prefix is already stating that these are bindings. See also: https://elixir.bootlin.com/linux/v6.17-rc3/source/Documentation/devicetree/bindings/submitting-patches.rst#L18 > slightly rearranged. Add a new binding file and compatible string > for version 8 using the name 'glymur' as the Qualcomm Technologies, > Inc. Glymur SoC is the first one to use PMIC arbiter version 8. This > specifies the new register ranges needed only for version 8. > > Signed-off-by: David Collins > Signed-off-by: Jishnu Prakash > Signed-off-by: Pankaj Patil > Signed-off-by: Kamal Wadhwa > --- > .../bindings/spmi/qcom,glymur-spmi-pmic-arb.yaml | 158 +++++++++++++++++++++ > 1 file changed, 158 insertions(+) > > diff --git a/Documentation/devicetree/bindings/spmi/qcom,glymur-spmi-pmic-arb.yaml b/Documentation/devicetree/bindings/spmi/qcom,glymur-spmi-pmic-arb.yaml > new file mode 100644 > index 0000000000000000000000000000000000000000..e80997a5fb4bcf59328e49c8b3e68c9511176a8c > --- /dev/null > +++ b/Documentation/devicetree/bindings/spmi/qcom,glymur-spmi-pmic-arb.yaml > @@ -0,0 +1,158 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/spmi/qcom,glymur-spmi-pmic-arb.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Technologies, Inc. Glymur SPMI Controller (PMIC Arbiter v8) > + > +maintainers: > + - Stephen Boyd I don't think so, why would Stephen care about Glymur? Did I miss some job change? And if I did not miss, then when you don't want to maintain your own stuff, neither we want. > + > +description: | > + The Glymur SPMI PMIC Arbiter implements HW version 8 and it's an SPMI > + controller with wrapping arbitration logic to allow for multiple on-chip > + devices to control up to 4 SPMI separate buses. > + > + The PMIC Arbiter can also act as an interrupt controller, providing interrupts > + to slave devices. > + > +properties: > + compatible: > + enum: > + - qcom,glymur-spmi-pmic-arb > + > + reg: > + items: > + - description: core registers > + - description: tx-channel per virtual slave registers > + - description: rx-channel (called observer) per virtual slave registers > + - description: channel to PMIC peripheral mapping registers > + > + reg-names: > + items: > + - const: core > + - const: chnls > + - const: obsrvr > + - const: chnl_map > + > + ranges: true > + > + '#address-cells': > + const: 2 > + > + '#size-cells': > + const: 2 > + > + qcom,ee: > + $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 0 > + maximum: 5 > + description: > Drop > > + indicates the active Execution Environment identifier > + > + qcom,channel: > + $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 0 > + maximum: 5 > + description: > Drop > > + which of the PMIC Arb provided channels to use for accesses > + Best regards, Krzysztof