From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D94FF2DC785; Tue, 14 Oct 2025 08:22:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760430138; cv=none; b=HGWxbYFULhwszGbG/pI96Vh5U6JNRJydlGz5U8y3UbYBO9u1CFSe7u9xPHf2xTM6kj4azKdepZk2W9UPkEIkzWRbddkP2DrqJiknTuWi6gpIolKfUdbKr8DcKhTaEfj8CtL9nTKkHlYQWx5IBu+7I5qO6C8SzW3wbG63nbQaYgc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760430138; c=relaxed/simple; bh=Vlj6tP3JBHPNk8PgyCr78TrY0haPC3Xs1lzW10Q8cLQ=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=ZkEkrWErCSMPH/V/KNXZgkuEqQoSZM8iGGtsvKNi0OMlVVtdd8kC9nkZKKkP27C3+t8XzIxMbW0WgK7CjwPWEbuOCOl+LVz/zlQ1m8Gpch+p6pMGBNvYf4iFcv2NQc17XcE/6l2pkaovvqHH7YBhJObhIOdTyWE65Tt+mS0W6Nk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lZh/f3/F; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lZh/f3/F" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6DC85C4CEE7; Tue, 14 Oct 2025 08:22:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1760430137; bh=Vlj6tP3JBHPNk8PgyCr78TrY0haPC3Xs1lzW10Q8cLQ=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=lZh/f3/Fc7dCqb6CDiY5tbcF9lWWIzM7REjTEic65K1WxpJhP9paD7iOWZjj/Y+Wl MCwhrgVrUc2HiR6nIBY2UXCxb516F1/kDTinX8shqb2b+g5M4vLRBCdRSl4DcAMq2D nv+FOWHFuTQ9tv3hmz509d6OyfqKZWSPJnWQWj7GHIamJEaCB/IEhdg2RUA8aNrrBi Ys+gVyn7W4USl4yzyKCR0gqCgiCDDZpRwP4v//qwyN4LOSSi2nIoFwj4nKBWBtP5Gp Lr0ploa3eB3xB+jXVL2E5QMpBE65dRCaLJ6CLKEffRcdnsBSSHGfpFt3trToDEUu6/ 8PgGVHCVqCkCw== Message-ID: Date: Tue, 14 Oct 2025 10:22:07 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/4] dt-bindings: usb: dwc3: Add Google Tensor G5 DWC3 To: Roy Luo Cc: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Thinh Nguyen , Philipp Zabel , Peter Griffin , =?UTF-8?Q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Joy Chakraborty , Naveen Kumar , Badhri Jagan Sridharan , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org References: <20251010201607.1190967-1-royluo@google.com> <20251010201607.1190967-2-royluo@google.com> <066a9598-ad30-4327-be68-87299bba6fda@kernel.org> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 8bit On 14/10/2025 03:40, Roy Luo wrote: > On Fri, Oct 10, 2025 at 5:09 PM Krzysztof Kozlowski wrote: >> >> On 10/10/2025 22:16, Roy Luo wrote: >>> Document the device tree bindings for the DWC3 USB controller found in >>> Google Tensor SoCs, starting with the G5 generation. >>> >>> The Tensor G5 silicon represents a complete architectural departure from >>> previous generations (like gs101), including entirely new clock/reset >>> schemes, top-level wrapper and register interface. Consequently, >>> existing Samsung/Exynos DWC3 USB bindings are incompatible, necessitating >>> this new device tree binding. >>> >>> The USB controller on Tensor G5 is based on Synopsys DWC3 IP and features >>> Dual-Role Device single port with hibernation support. >> >> You still mix, completely unnecessarily, subsystems. For Greg this is >> actually even undesired, but regardless don't do this for any cases >> because it just makes everything slower or more difficult to apply. >> >> Really, think how maintainers should deal with your patches. >> > > Understood, I will separate the patches into two distinct series: one for > the controller and one for the PHY. > Appreciate the feedback and the explanation. > >>> >>> Signed-off-by: Roy Luo >>> --- >>> .../bindings/usb/google,gs5-dwc3.yaml | 141 ++++++++++++++++++ >>> 1 file changed, 141 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml >>> >>> diff --git a/Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml b/Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml >>> new file mode 100644 >>> index 000000000000..6fadea7f41e8 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml >>> @@ -0,0 +1,141 @@ >>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >>> +# Copyright (c) 2025, Google LLC >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/usb/google,gs5-dwc3.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Google Tensor Series (G5+) DWC3 USB SoC Controller >>> + >>> +maintainers: >>> + - Roy Luo >>> + >>> +description: >>> + Describes the DWC3 USB controller block implemented on Google Tensor SoCs, >>> + starting with the G5 generation. Based on Synopsys DWC3 IP, the controller >>> + features Dual-Role Device single port with hibernation add-on. >>> + >>> +properties: >>> + compatible: >>> + const: google,gs5-dwc3 >>> + >>> + reg: >>> + items: >>> + - description: Core DWC3 IP registers. >>> + - description: USB host controller configuration registers. >>> + - description: USB custom interrrupts control registers. >>> + >>> + reg-names: >>> + items: >>> + - const: dwc3_core >>> + - const: host_cfg >>> + - const: usbint_cfg >>> + >>> + interrupts: >>> + items: >>> + - description: Core DWC3 interrupt. >>> + - description: High speed power management event for remote wakeup from hibernation. >>> + - description: Super speed power management event for remote wakeup from hibernation. >> >> Wrap at 80 (see coding style) or just shorten these. > > Ack, will fix it in the next patch. > >> >>> + >>> + interrupt-names: >>> + items: >>> + - const: dwc_usb3 >> >> So just "core"? > > I'd prefer to stick to "dwc_usb3" as that's > 1. more expressive by referring to the underlying IP name, But that's completely redundant name. > 2. consistent with established dwc3 bindings such as > Documentation/devicetree/bindings/usb/snps,dwc3.yaml, If you use only one interrupt. You don't use one interrupt here. > Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml, > unless you have a strong preference for the alternative naming. Such namings are discouraged, because they tell absolutely nothing. Also, schematics or datasheets usually do not use them, either. Best regards, Krzysztof