From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: Krzysztof Kozlowski <krzk@kernel.org>,
Laura Nao <laura.nao@collabora.com>,
mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com,
p.zabel@pengutronix.de, richardcochran@gmail.com
Cc: guangjie.song@mediatek.com, wenst@chromium.org,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, netdev@vger.kernel.org,
kernel@collabora.com
Subject: Re: [PATCH 30/30] clk: mediatek: mt8196: Add UFS and PEXTP0/1 reset controllers
Date: Mon, 23 Jun 2025 14:33:24 +0200 [thread overview]
Message-ID: <b7b78f8c-b70f-424c-90b8-eeb0eda50041@collabora.com> (raw)
In-Reply-To: <d1802074-5472-475c-94b6-a0667e353208@kernel.org>
Il 23/06/25 14:14, Krzysztof Kozlowski ha scritto:
> On 23/06/2025 12:29, Laura Nao wrote:
>> From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>>
>> Add definitions to register the reset controllers found in the
>> UFS and PEXTP clock controllers.
>>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> Signed-off-by: Laura Nao <laura.nao@collabora.com>
>> ---
>> drivers/clk/mediatek/clk-mt8196-pextp.c | 36 ++++++++++++++++++++++++
>> drivers/clk/mediatek/clk-mt8196-ufs_ao.c | 25 ++++++++++++++++
>> 2 files changed, 61 insertions(+)
>
> You just added these files. Don't add incomplete driver just to fix it
> later. Add complete driver.
>
> Patch should be squashed.
Laura, feel free to squash the patches.
Cheers,
Angelo
>
> Best regards,
> Krzysztof
next prev parent reply other threads:[~2025-06-23 12:33 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-23 10:29 [PATCH 00/30] Add support for MT8196 clock controllers Laura Nao
2025-06-23 10:29 ` [PATCH 01/30] clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable control Laura Nao
2025-06-23 10:29 ` [PATCH 02/30] clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENC Laura Nao
2025-06-23 10:29 ` [PATCH 03/30] clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd " Laura Nao
2025-06-23 10:29 ` [PATCH 04/30] clk: mediatek: clk-mtk: Introduce mtk_clk_get_hwv_regmap() Laura Nao
2025-06-23 10:29 ` [PATCH 05/30] clk: mediatek: clk-mux: Add ops for mux gates with HW voter and FENC Laura Nao
2025-06-23 10:29 ` [PATCH 06/30] clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk_gate struct Laura Nao
2025-06-23 10:29 ` [PATCH 07/30] clk: mediatek: clk-gate: Add ops for gates with HW voter Laura Nao
2025-06-23 10:29 ` [PATCH 08/30] clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro Laura Nao
2025-06-23 10:29 ` [PATCH 09/30] dt-bindings: clock: mediatek: Describe MT8196 peripheral clock controllers Laura Nao
2025-06-23 12:12 ` Krzysztof Kozlowski
2025-06-23 12:28 ` AngeloGioacchino Del Regno
2025-06-23 10:29 ` [PATCH 10/30] clk: mediatek: Add MT8196 apmixedsys clock support Laura Nao
2025-06-23 10:29 ` [PATCH 11/30] clk: mediatek: Add MT8196 topckgen " Laura Nao
2025-06-23 10:29 ` [PATCH 12/30] clk: mediatek: Add MT8196 topckgen2 " Laura Nao
2025-06-23 10:29 ` [PATCH 13/30] clk: mediatek: Add MT8196 vlpckgen " Laura Nao
2025-06-23 10:29 ` [PATCH 14/30] clk: mediatek: Add MT8196 peripheral " Laura Nao
2025-06-23 10:29 ` [PATCH 15/30] clk: mediatek: Add MT8196 ufssys " Laura Nao
2025-06-23 10:29 ` [PATCH 16/30] clk: mediatek: Add MT8196 pextpsys " Laura Nao
2025-06-23 10:29 ` [PATCH 17/30] clk: mediatek: Add MT8196 adsp " Laura Nao
2025-06-23 10:29 ` [PATCH 18/30] clk: mediatek: Add MT8196 I2C " Laura Nao
2025-06-23 10:29 ` [PATCH 19/30] clk: mediatek: Add MT8196 mcu " Laura Nao
2025-06-23 10:29 ` [PATCH 20/30] clk: mediatek: Add MT8196 mdpsys " Laura Nao
2025-06-23 10:29 ` [PATCH 21/30] clk: mediatek: Add MT8196 mfg " Laura Nao
2025-06-23 10:29 ` [PATCH 22/30] clk: mediatek: Add MT8196 disp0 " Laura Nao
2025-06-23 10:29 ` [PATCH 23/30] clk: mediatek: Add MT8196 disp1 " Laura Nao
2025-06-23 10:29 ` [PATCH 24/30] clk: mediatek: Add MT8196 disp-ao " Laura Nao
2025-06-24 6:40 ` kernel test robot
2025-06-23 10:29 ` [PATCH 25/30] clk: mediatek: Add MT8196 ovl0 " Laura Nao
2025-06-23 10:29 ` [PATCH 26/30] clk: mediatek: Add MT8196 ovl1 " Laura Nao
2025-06-23 10:29 ` [PATCH 27/30] clk: mediatek: Add MT8196 vdecsys " Laura Nao
2025-06-23 10:29 ` [PATCH 28/30] clk: mediatek: Add MT8196 vencsys " Laura Nao
2025-06-23 10:29 ` [PATCH 29/30] dt-bindings: reset: Add MediaTek MT8196 Reset Controller binding Laura Nao
2025-06-23 12:13 ` Krzysztof Kozlowski
2025-06-23 12:22 ` AngeloGioacchino Del Regno
2025-06-23 10:29 ` [PATCH 30/30] clk: mediatek: mt8196: Add UFS and PEXTP0/1 reset controllers Laura Nao
2025-06-23 12:14 ` Krzysztof Kozlowski
2025-06-23 12:33 ` AngeloGioacchino Del Regno [this message]
2025-06-23 11:34 ` [PATCH 00/30] Add support for MT8196 clock controllers AngeloGioacchino Del Regno
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