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[188.141.3.146]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45b7e898b99sm287110985e9.19.2025.09.04.07.55.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 04 Sep 2025 07:55:13 -0700 (PDT) Message-ID: Date: Thu, 4 Sep 2025 15:55:09 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/5] i2c: qcom-cci: Add OPP table support and enforce FAST_PLUS requirements To: Konrad Dybcio , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Loic Poulain , Robert Foss , Andi Shyti Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, Konrad Dybcio References: <20250904-topic-cci_updates-v1-0-d38559692703@oss.qualcomm.com> <20250904-topic-cci_updates-v1-4-d38559692703@oss.qualcomm.com> From: Bryan O'Donoghue Content-Language: en-US In-Reply-To: <20250904-topic-cci_updates-v1-4-d38559692703@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 04/09/2025 15:31, Konrad Dybcio wrote: > From: Konrad Dybcio > > The CCI clock has voltage requirements, which need to be described > through an OPP table. > > The 1 MHz FAST_PLUS mode requires the CCI core clock runs at 37,5 MHz > (which is a value common across all SoCs), since it's not possible to > reach the required timings with the default 19.2 MHz rate. > > Address both issues by introducing an OPP table and using it to vote > for the faster rate. > > Signed-off-by: Konrad Dybcio > --- > drivers/i2c/busses/i2c-qcom-cci.c | 33 +++++++++++++++++++++++++++++++++ > 1 file changed, 33 insertions(+) > > diff --git a/drivers/i2c/busses/i2c-qcom-cci.c b/drivers/i2c/busses/i2c-qcom-cci.c > index 74fedfdec3ae4e034ec4d946179e963c783b5923..d6192e2a5e3bc4d908cba594d1910a41f3a41e9c 100644 > --- a/drivers/i2c/busses/i2c-qcom-cci.c > +++ b/drivers/i2c/busses/i2c-qcom-cci.c > @@ -10,6 +10,7 @@ > #include > #include > #include > +#include > #include > > #define CCI_HW_VERSION 0x0 > @@ -121,6 +122,7 @@ struct cci_data { > struct i2c_adapter_quirks quirks; > u16 queue_size[NUM_QUEUES]; > struct hw_params params[3]; > + bool fast_mode_plus_supported; that is a very long name for a flag > }; > > struct cci { > @@ -466,9 +468,22 @@ static const struct i2c_algorithm cci_algo = { > .functionality = cci_func, > }; > > +static unsigned long cci_desired_clk_rate(struct cci *cci) > +{ > + if (cci->data->fast_mode_plus_supported) > + return 37500000ULL; > + > + return 19200000ULL; what's 32 bits between friends ? > +} > + > static int __maybe_unused cci_suspend_runtime(struct device *dev) > { > struct cci *cci = dev_get_drvdata(dev); > + int ret; > + > + ret = dev_pm_opp_set_rate(dev, 0); > + if (ret) > + return ret; > > clk_bulk_disable_unprepare(cci->nclocks, cci->clocks); > > @@ -484,6 +499,10 @@ static int __maybe_unused cci_resume_runtime(struct device *dev) > if (ret) > return ret; > > + ret = dev_pm_opp_set_rate(dev, cci_desired_clk_rate(cci)); > + if (ret) > + return ret; > + > cci_init(cci); > > return 0; > @@ -588,6 +607,19 @@ static int cci_probe(struct platform_device *pdev) > if (ret < 0) > return ret; > > + ret = devm_pm_opp_set_clkname(dev, "cci"); > + if (ret) > + return ret; > + > + /* OPP table is optional */ > + ret = devm_pm_opp_of_add_table(dev); > + if (ret && ret != -ENODEV) > + return dev_err_probe(dev, ret, "invalid OPP table in device tree\n"); > + > + ret = dev_pm_opp_set_rate(dev, cci_desired_clk_rate(cci)); > + if (ret) > + return ret; > + > /* Interrupt */ > > ret = platform_get_irq(pdev, 0); > @@ -775,6 +807,7 @@ static const struct cci_data cci_v2_data = { > .trdhld = 3, > .tsp = 3 > }, > + .fast_mode_plus_supported = true, > }; > > static const struct of_device_id cci_dt_match[] = { > LGTM Reviewed-by: Bryan O'Donoghue