From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBE6723EAB7; Tue, 28 Apr 2026 13:12:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777381935; cv=none; b=B1q3ddsG1rrnOfh3CN39inAZr/Qtef93DOevV3vR1xlL+nw80H4GLymE0R1lMl34TweOA3lh1P2PCqMAICrpmSWjk9GhLAihVcKBM7hagnt5iXqnDjs0HkNZI66SZysM7HThhpR6Zw9tckE+wiToooGHkOKaiZkJiKiOw9ag6VY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777381935; c=relaxed/simple; bh=oW56JoPmFIS1i2yPhNaXLijroc14e37zIFPihlQOMSU=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=k/3lS8gE8Qn8TBJ8XupAsWEVNTyOav5tKDNWt5eXbZ6fM5md8oh/El3p2Cf+PNR9llUijB9ukCJQY6/yNEkNfH8fWVPRaz7hks4+7Uq3b2kfG1zvh+51fbrRn5siskwoC0Z8K86cXag9oAWJNA6hm2ZlybDNToTjL0dDvxRERdc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ElKJwPIm; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ElKJwPIm" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C0C66C2BCAF; Tue, 28 Apr 2026 13:12:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777381935; bh=oW56JoPmFIS1i2yPhNaXLijroc14e37zIFPihlQOMSU=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=ElKJwPImf5Upii6Z79TOzchXD4rG6CnZVMUQ2QQG+VXiUGjoBJMYbeJNod9IEIwCC XR3Hne61aEXBi4F0nyqMxOmfsW67bXBfkFhqkULD1E/aLnr5ZGxVrZYblqfsiXJnZu FXaSoZprxKSmiLXKH4Uo5HTkpHqK3b/2+MWaOJ4Ku7Kqai6/mesbDzeumkmvpXADXW 099r/HXbLZ9/BaydnVQWR6UW1SLgMciAGuSD5Uk6250KwUBNCZ3nj/sI940B2OxEr6 uAZOWhg5wXfR3PAtVeu6PjtKOuitgipATKnp1uC6cgJpCuYWFyqsSD7NyAWI02rETi f0yl4eZYYiD9Q== Message-ID: Date: Tue, 28 Apr 2026 15:12:11 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/2] dt-bindings: remoteproc: document AMD BRAM-based rproc To: Michal Simek , Ben Levinsky Cc: andersson@kernel.org, mathieu.poirier@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, tanmay.shah@amd.com References: <20260427162703.1644103-1-ben.levinsky@amd.com> <20260427162703.1644103-2-ben.levinsky@amd.com> <20260428-curly-hyena-of-triumph-fc1f4c@quoll> <68cf4479-c6f5-4947-bc75-df9be73644d3@amd.com> <998b67ff-192a-478f-a9c6-ddcd7773e27c@kernel.org> <86e464f2-974b-441d-9459-dd957c16993d@amd.com> <5ded8bbd-11b2-4552-80f5-972df15dc6e0@kernel.org> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 28/04/2026 15:09, Michal Simek wrote: > > > On 4/28/26 11:14, Krzysztof Kozlowski wrote: >> On 28/04/2026 11:04, Michal Simek wrote: >>> >>> >>> On 4/28/26 10:47, Krzysztof Kozlowski wrote: >>>> On 28/04/2026 10:33, Michal Simek wrote: >>>>> >>>>> >>>>> On 4/28/26 08:50, Krzysztof Kozlowski wrote: >>>>>> On Mon, Apr 27, 2026 at 09:27:02AM -0700, Ben Levinsky wrote: >>>>>>> Describe an AMD BRAM-based soft-core processor subsystem instantiated in >>>>>>> programmable logic and using dual-port BRAM for firmware storage and >>>>>>> execution. >>>>>>> >>>>>>> The binding models a soft-core processor subsystem instantiated in AMD >>>>>>> programmable logic and using dual-port BRAM for firmware storage and >>>>>>> execution. The remoteproc device is represented as a child node whose >>>>>>> reg property describes the firmware memory window in the processor-local >>>>>>> address space. The parent bus node provides standard devicetree address >>>>>>> translation through ranges so Linux can access the same BRAM through the >>>>>>> system physical address space. >>>>>>> >>>>>>> A clock input feeds the soft-core processor subsystem, and an active-low >>>>>>> reset GPIO holds the processor in reset until firmware loading >>>>>>> completes. The firmware-name property is optional. >>>>>>> >>>>>>> Signed-off-by: Ben Levinsky >>>>>>> --- >>>>>>> .../bindings/remoteproc/amd,bram-rproc.yaml | 98 +++++++++++++++++++ >>>>>>> 1 file changed, 98 insertions(+) >>>>>>> create mode 100644 Documentation/devicetree/bindings/remoteproc/amd,bram-rproc.yaml >>>>>>> >>>>>>> diff --git a/Documentation/devicetree/bindings/remoteproc/amd,bram-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/amd,bram-rproc.yaml >>>>>>> new file mode 100644 >>>>>>> index 000000000000..f16657dc0d9f >>>>>>> --- /dev/null >>>>>>> +++ b/Documentation/devicetree/bindings/remoteproc/amd,bram-rproc.yaml >>>>>>> @@ -0,0 +1,98 @@ >>>>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>>>>>> +%YAML 1.2 >>>>>>> +--- >>>>>>> +$id: http://devicetree.org/schemas/remoteproc/amd,bram-rproc.yaml# >>>>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>>>>>> + >>>>>>> +title: AMD BRAM-based Remote Processor >>>>>>> + >>>>>>> +maintainers: >>>>>>> + - Ben Levinsky >>>>>>> + >>>>>>> +description: | >>>>>>> + Soft-core processor subsystem instantiated in AMD programmable logic and >>>>>>> + using dual-port BRAM for firmware storage and execution. >>>>>> >>>>>> Isn't the soft-core or FPGA still part of some Xilinx SoC? Or is this >>>>>> completely different thing from SoC and there is a design WITHOUT SoC >>>>>> using this remote proc? >>>>> >>>>> In 99% case this is going to be used on Xilinx SOC with programmable logic next >>>>> to ARM core. >>>>> soft core means - means VHDL/Verilog code synthesized to programmable >>>>> logic/fpga. It means exact location in chip varies based on build and constraints. >>>>> >>>>> hard core - physical HW location - like ARM cores in our chip. >>>>> >>>>> (ARM is providing RTL/code that even ARM cores in fpga emulated platforms are >>>>> actually used as soft cores). >>>>> >>>>> Not sure if you want me to talk about that 1% use cases which are also possible >>>>> but don't think anybody will design them. >>>> >>>> Then I would treat it exactly like every other block of a SoC - you need >>>> a SoC specific compatible. If there is a fallback, SoC specific >>>> compatible should be used in the fallback as well - that's all already >>>> documented in writing-bindings. >>> >>> But which SOC? We have ZynqMP, Versal, Versal NET, Versal Gen 2. And all of >>> these will use this configuration. >>> Do you want to list all of them? >> >> "Then I would treat it exactly like every other block of a SoC" > > No issue. Here is snippet. > > properties: > compatible: > items: > - enum: > - xlnx,zynqmp-bram-rproc > - xlnx,versal-bram-rproc > - xlnx,versal-net-bram-rproc > - amd,versal2-bram-rproc > - const: amd,bram-rproc > > The example should also be updated: Yes, except what I wrote earlier and is mentioned in the writing bindings doc - the specific compatible should be also the fallback. Best regards, Krzysztof