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[83.9.32.53]) by smtp.gmail.com with ESMTPSA id p6-20020a2ea406000000b00289cfd2088csm693673ljn.73.2023.01.13.07.20.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 13 Jan 2023 07:20:08 -0800 (PST) Message-ID: Date: Fri, 13 Jan 2023 16:20:06 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH 6/6] clk: qcom: Fix APSS PLL and RCG Configuration Content-Language: en-US To: devi priya , agross@kernel.org, andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, jassisinghbrar@gmail.com, catalin.marinas@arm.com, will@kernel.org, shawnguo@kernel.org, arnd@arndb.de, marcel.ziswiler@toradex.com, dmitry.baryshkov@linaro.org, nfraprado@collabora.com, broonie@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: quic_srichara@quicinc.com, quic_gokulsri@quicinc.com, quic_sjaganat@quicinc.com, quic_kathirav@quicinc.com, quic_arajkuma@quicinc.com, quic_anusha@quicinc.com, quic_poovendh@quicinc.com References: <20230113143647.14961-1-quic_devipriy@quicinc.com> <20230113143647.14961-7-quic_devipriy@quicinc.com> From: Konrad Dybcio In-Reply-To: <20230113143647.14961-7-quic_devipriy@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 13.01.2023 15:36, devi priya wrote: > Included CLK_IS_CRITICAL flag which helps to properly enable > the APSS PLL during bootup. Please describe the issue and not only the user-visible impact it makes. Does the PLL get shut down by clk_ignore_unused? Maybe you would be interested in the sync_state changes that landed in recent -next that may solve it for you? I don't think it should be always-on, as you have an alternate source for low power modes, adding CLK_IS_CRITICAL will keep the PLL enabled even if you're not using it. > clk_rcg2_ops should be used for APSS clock RCG, as other ops > will not configure the RCG register RCG register meaning RCG register*s*, meaning in this case M/N/D which would be required for proper rate setting and not only input switching (which arguably doesn't seem to be of much concern on a single-parent clock)? This all is not obvious.. Konrad > > Co-developed-by: Praveenkumar I > Signed-off-by: Praveenkumar I > Signed-off-by: devi priya > --- > drivers/clk/qcom/apss-ipq-pll.c | 1 + > drivers/clk/qcom/apss-ipq6018.c | 8 +++++++- > 2 files changed, 8 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c > index dd0c01bf5a98..75486a124fcd 100644 > --- a/drivers/clk/qcom/apss-ipq-pll.c > +++ b/drivers/clk/qcom/apss-ipq-pll.c > @@ -33,6 +33,7 @@ static struct clk_alpha_pll ipq_pll = { > }, > .num_parents = 1, > .ops = &clk_alpha_pll_huayra_ops, > + .flags = CLK_IS_CRITICAL, > }, > }, > }; > diff --git a/drivers/clk/qcom/apss-ipq6018.c b/drivers/clk/qcom/apss-ipq6018.c > index f2f502e2d5a4..0d0e7196a4dc 100644 > --- a/drivers/clk/qcom/apss-ipq6018.c > +++ b/drivers/clk/qcom/apss-ipq6018.c > @@ -33,15 +33,21 @@ static const struct parent_map parents_apcs_alias0_clk_src_map[] = { > { P_APSS_PLL_EARLY, 5 }, > }; > > +static const struct freq_tbl ftbl_apcs_alias0_clk_src[] = { > + { .src = P_APSS_PLL_EARLY, .pre_div = 1 }, > + { } > +}; > + > static struct clk_rcg2 apcs_alias0_clk_src = { > .cmd_rcgr = 0x0050, > + .freq_tbl = ftbl_apcs_alias0_clk_src, > .hid_width = 5, > .parent_map = parents_apcs_alias0_clk_src_map, > .clkr.hw.init = &(struct clk_init_data){ > .name = "apcs_alias0_clk_src", > .parent_data = parents_apcs_alias0_clk_src, > .num_parents = ARRAY_SIZE(parents_apcs_alias0_clk_src), > - .ops = &clk_rcg2_mux_closest_ops, > + .ops = &clk_rcg2_ops, > .flags = CLK_SET_RATE_PARENT, > }, > };