[PATCH v2 0/2] dt-bindings: clock: xilinx: Update VCU bindings

[PATCH v2 0/2] dt-bindings: clock: xilinx: Update VCU bindings

[Rohit Visavalia]

This patch series converts dt-binding to dtschema and adds reset GPIO
as optional property. 

---
Changes in v2:
  - dropped patch 1 and move the file during conversion
  - dropped description in schema
  - updated commit msg for change in clock ordering
  - used decimal number for GPIO

Link to v1: https://lore.kernel.org/linux-clk/20250102163700.759712-1-rohit.visavalia@amd.com/

Rohit Visavalia (2):
  dt-bindings: clock: xilinx: Convert VCU bindings to dtschema
  dt-bindings: clock: xilinx: Add reset GPIO for VCU

 .../devicetree/bindings/clock/xlnx,vcu.yaml   | 59 +++++++++++++++++++
 .../bindings/soc/xilinx/xlnx,vcu.txt          | 26 --------
 2 files changed, 59 insertions(+), 26 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/xlnx,vcu.yaml
 delete mode 100644 Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt

-- 
2.25.1

[PATCH v2 1/2] dt-bindings: clock: xilinx: Convert VCU bindings to dtschema

[Rohit Visavalia]

From: Rohit Visavalia <rohit.visavalia@xilinx.com>

Convert AMD (Xilinx) VCU bindings to yaml format.
Additional changes:
   - move xlnx_vcu DT binding to clock from soc following commit
     a2fe7baa27a4 ("clk: xilinx: move xlnx_vcu clock driver from soc")
   - corrected clock sequence as per xilinx device-tree generator

Signed-off-by: Rohit Visavalia <rohit.visavalia@xilinx.com>

---
Changes in v2:
  - dropped patch 1 and move the file during conversion
  - dropped description in schema
  - updated commit msg for change in clock ordering

---
 .../devicetree/bindings/clock/xlnx,vcu.yaml   | 55 +++++++++++++++++++
 .../bindings/soc/xilinx/xlnx,vcu.txt          | 26 ---------
 2 files changed, 55 insertions(+), 26 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/xlnx,vcu.yaml
 delete mode 100644 Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt

diff --git a/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml b/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml
new file mode 100644
index 000000000000..02d27d11a452
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/xlnx,vcu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: LogicoreIP designed compatible with Xilinx ZYNQ family.
+
+maintainers:
+  - Rohit Visavalia <rohit.visavalia@amd.com>
+
+description:
+  LogicoreIP design to provide the isolation between processing system
+  and programmable logic. Also provides the list of register set to configure
+  the frequency.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - xlnx,vcu
+          - xlnx,vcu-logicoreip-1.0
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: pll ref clocksource
+      - description: aclk
+
+  clock-names:
+    items:
+      - const: pll_ref
+      - const: aclk
+
+required:
+  - reg
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+    fpga {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        xlnx_vcu: vcu@a0040000 {
+            compatible = "xlnx,vcu-logicoreip-1.0";
+            reg = <0x0 0xa0040000 0x0 0x1000>;
+            clocks = <&si570_1>, <&clkc 71>;
+            clock-names = "pll_ref", "aclk";
+        };
+    };
diff --git a/Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt b/Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt
deleted file mode 100644
index 2417b13ba468..000000000000
--- a/Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-LogicoreIP designed compatible with Xilinx ZYNQ family.
--------------------------------------------------------
-
-General concept
----------------
-
-LogicoreIP design to provide the isolation between processing system
-and programmable logic. Also provides the list of register set to configure
-the frequency.
-
-Required properties:
-- compatible: shall be one of:
-	"xlnx,vcu"
-	"xlnx,vcu-logicoreip-1.0"
-- reg : The base offset and size of the VCU_PL_SLCR register space.
-- clocks: phandle for aclk and pll_ref clocksource
-- clock-names: The identification string, "aclk", is always required for
-   the axi clock. "pll_ref" is required for pll.
-Example:
-
-	xlnx_vcu: vcu@a0040000 {
-		compatible = "xlnx,vcu-logicoreip-1.0";
-		reg = <0x0 0xa0040000 0x0 0x1000>;
-		clocks = <&si570_1>, <&clkc 71>;
-		clock-names = "pll_ref", "aclk";
-	};
-- 
2.25.1

[PATCH v2 2/2] dt-bindings: clock: xilinx: Add reset GPIO for VCU

[Rohit Visavalia]

It is marked as optional as some of the ZynqMP designs are having vcu_reset
(reset pin of VCU IP) driven by proc_sys_reset, proc_sys_reset is another
PL IP driven by the PS pl_reset. So, here the VCU reset is not driven by
axi_gpio or PS GPIO so there will be no GPIO entry.

Signed-off-by: Rohit Visavalia <rohit.visavalia@amd.com>
---
Changes in v2:
  - dropped description GPIO property
  - used decimal number for GPIO

---
 Documentation/devicetree/bindings/clock/xlnx,vcu.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml b/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml
index 02d27d11a452..19dc923e2ee9 100644
--- a/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml
+++ b/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml
@@ -33,6 +33,9 @@ properties:
       - const: pll_ref
       - const: aclk
 
+  reset-gpios:
+    maxItems: 1
+
 required:
   - reg
   - clocks
@@ -49,6 +52,7 @@ examples:
         xlnx_vcu: vcu@a0040000 {
             compatible = "xlnx,vcu-logicoreip-1.0";
             reg = <0x0 0xa0040000 0x0 0x1000>;
+            reset-gpios = <&gpio 78 GPIO_ACTIVE_HIGH>;
             clocks = <&si570_1>, <&clkc 71>;
             clock-names = "pll_ref", "aclk";
         };
-- 
2.25.1

Re: [PATCH v2 1/2] dt-bindings: clock: xilinx: Convert VCU bindings to dtschema

[Krzysztof Kozlowski]

On Mon, Jan 06, 2025 at 08:40:37PM -0800, Rohit Visavalia wrote:
> From: Rohit Visavalia <rohit.visavalia@xilinx.com>
> 
> Convert AMD (Xilinx) VCU bindings to yaml format.
> Additional changes:
>    - move xlnx_vcu DT binding to clock from soc following commit
>      a2fe7baa27a4 ("clk: xilinx: move xlnx_vcu clock driver from soc")
>    - corrected clock sequence as per xilinx device-tree generator
> 
> Signed-off-by: Rohit Visavalia <rohit.visavalia@xilinx.com>
> 

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v2 2/2] dt-bindings: clock: xilinx: Add reset GPIO for VCU

[Krzysztof Kozlowski]

On Mon, Jan 06, 2025 at 08:40:38PM -0800, Rohit Visavalia wrote:
> It is marked as optional as some of the ZynqMP designs are having vcu_reset
> (reset pin of VCU IP) driven by proc_sys_reset, proc_sys_reset is another
> PL IP driven by the PS pl_reset. So, here the VCU reset is not driven by
> axi_gpio or PS GPIO so there will be no GPIO entry.
> 
> Signed-off-by: Rohit Visavalia <rohit.visavalia@amd.com>
> ---
> Changes in v2:
>   - dropped description GPIO property
>   - used decimal number for GPIO
> 

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v2 1/2] dt-bindings: clock: xilinx: Convert VCU bindings to dtschema

[Stephen Boyd]

Quoting Rohit Visavalia (2025-01-06 20:40:37)
> From: Rohit Visavalia <rohit.visavalia@xilinx.com>
> 
> Convert AMD (Xilinx) VCU bindings to yaml format.
> Additional changes:
>    - move xlnx_vcu DT binding to clock from soc following commit
>      a2fe7baa27a4 ("clk: xilinx: move xlnx_vcu clock driver from soc")
>    - corrected clock sequence as per xilinx device-tree generator
> 
> Signed-off-by: Rohit Visavalia <rohit.visavalia@xilinx.com>
> 
> ---

Applied to clk-next

Re: [PATCH v2 2/2] dt-bindings: clock: xilinx: Add reset GPIO for VCU

[Stephen Boyd]

Quoting Rohit Visavalia (2025-01-06 20:40:38)
> It is marked as optional as some of the ZynqMP designs are having vcu_reset
> (reset pin of VCU IP) driven by proc_sys_reset, proc_sys_reset is another
> PL IP driven by the PS pl_reset. So, here the VCU reset is not driven by
> axi_gpio or PS GPIO so there will be no GPIO entry.
> 
> Signed-off-by: Rohit Visavalia <rohit.visavalia@amd.com>
> ---

Applied to clk-next