Re: [PATCH v2 2/3] arm64: dts: qcom: sm8650: add CPU cache size properties

Konrad Dybcio
2026-04-21T10:42:53Z

On 4/20/26 9:26 PM, Neil Armstrong wrote:
> Add the L1 cache size and its line size (cache-size and
> cache-line-size) with the corresponding L1-I cache and L1-D cache.
>
> L1 cache is unified, but clidr_el1 register (get_cache_type) tells that
> L1 cache is separated (CACHE_TYPE_SEPARATE), add i-cache-line-size and
> d-cache-line-size and cache-line-size of L3 cache is specified.
>
> All cache line sizes were confirmed by checking ccsidr_el1.
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad