* [PATCH 1/5] dt-bindings: i2c: qcom-cci: Document sc8280xp compatible
2023-10-06 12:01 [PATCH 0/5] Add sc8280xp CCI and CAMSS core dtsi Bryan O'Donoghue
@ 2023-10-06 12:01 ` Bryan O'Donoghue
2023-10-06 12:29 ` Krzysztof Kozlowski
2023-10-10 19:44 ` Wolfram Sang
2023-10-06 12:01 ` [PATCH 2/5] i2c: qcom-cci: Add " Bryan O'Donoghue
` (3 subsequent siblings)
4 siblings, 2 replies; 20+ messages in thread
From: Bryan O'Donoghue @ 2023-10-06 12:01 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, loic.poulain, rfoss, andi.shyti,
robh+dt, krzysztof.kozlowski+dt, conor+dt, todor.too, mchehab,
bryan.odonoghue
Cc: linux-arm-msm, linux-i2c, linux-media, devicetree, linux-kernel
Add sc8280xp compatible consistent with recent CAMSS CCI interfaces.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
index 042d4dc636ee..8a8d0a01017c 100644
--- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
+++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
@@ -25,6 +25,7 @@ properties:
- items:
- enum:
+ - qcom,sc8280xp-cci
- qcom,sdm845-cci
- qcom,sm6350-cci
- qcom,sm8250-cci
@@ -159,6 +160,7 @@ allOf:
compatible:
contains:
enum:
+ - qcom,sc8280xp-cci
- qcom,sm8250-cci
- qcom,sm8450-cci
then:
--
2.40.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH 1/5] dt-bindings: i2c: qcom-cci: Document sc8280xp compatible
2023-10-06 12:01 ` [PATCH 1/5] dt-bindings: i2c: qcom-cci: Document sc8280xp compatible Bryan O'Donoghue
@ 2023-10-06 12:29 ` Krzysztof Kozlowski
2023-10-10 19:44 ` Wolfram Sang
1 sibling, 0 replies; 20+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-06 12:29 UTC (permalink / raw)
To: Bryan O'Donoghue, agross, andersson, konrad.dybcio,
loic.poulain, rfoss, andi.shyti, robh+dt, krzysztof.kozlowski+dt,
conor+dt, todor.too, mchehab
Cc: linux-arm-msm, linux-i2c, linux-media, devicetree, linux-kernel
On 06/10/2023 14:01, Bryan O'Donoghue wrote:
> Add sc8280xp compatible consistent with recent CAMSS CCI interfaces.
>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 1/5] dt-bindings: i2c: qcom-cci: Document sc8280xp compatible
2023-10-06 12:01 ` [PATCH 1/5] dt-bindings: i2c: qcom-cci: Document sc8280xp compatible Bryan O'Donoghue
2023-10-06 12:29 ` Krzysztof Kozlowski
@ 2023-10-10 19:44 ` Wolfram Sang
2023-10-10 22:25 ` Bryan O'Donoghue
1 sibling, 1 reply; 20+ messages in thread
From: Wolfram Sang @ 2023-10-10 19:44 UTC (permalink / raw)
To: Bryan O'Donoghue
Cc: agross, andersson, konrad.dybcio, loic.poulain, rfoss, andi.shyti,
robh+dt, krzysztof.kozlowski+dt, conor+dt, todor.too, mchehab,
linux-arm-msm, linux-i2c, linux-media, devicetree, linux-kernel
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On Fri, Oct 06, 2023 at 01:01:55PM +0100, Bryan O'Donoghue wrote:
> Add sc8280xp compatible consistent with recent CAMSS CCI interfaces.
>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Applied to for-next, thanks!
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 1/5] dt-bindings: i2c: qcom-cci: Document sc8280xp compatible
2023-10-10 19:44 ` Wolfram Sang
@ 2023-10-10 22:25 ` Bryan O'Donoghue
2023-10-11 6:28 ` Wolfram Sang
0 siblings, 1 reply; 20+ messages in thread
From: Bryan O'Donoghue @ 2023-10-10 22:25 UTC (permalink / raw)
To: Wolfram Sang, agross, andersson, konrad.dybcio, loic.poulain,
rfoss, andi.shyti, robh+dt, krzysztof.kozlowski+dt, conor+dt,
todor.too, mchehab, linux-arm-msm, linux-i2c, linux-media,
devicetree, linux-kernel
On 10/10/2023 20:44, Wolfram Sang wrote:
> On Fri, Oct 06, 2023 at 01:01:55PM +0100, Bryan O'Donoghue wrote:
>> Add sc8280xp compatible consistent with recent CAMSS CCI interfaces.
>>
>> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
>
> Applied to for-next, thanks!
>
Hey Wolfram.
This patch was superseded could you please drop ?
https://lore.kernel.org/linux-arm-msm/20231010122539.1768825-1-bryan.odonoghue@linaro.org/
---
bod
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 1/5] dt-bindings: i2c: qcom-cci: Document sc8280xp compatible
2023-10-10 22:25 ` Bryan O'Donoghue
@ 2023-10-11 6:28 ` Wolfram Sang
0 siblings, 0 replies; 20+ messages in thread
From: Wolfram Sang @ 2023-10-11 6:28 UTC (permalink / raw)
To: Bryan O'Donoghue
Cc: agross, andersson, konrad.dybcio, loic.poulain, rfoss, andi.shyti,
robh+dt, krzysztof.kozlowski+dt, conor+dt, todor.too, mchehab,
linux-arm-msm, linux-i2c, linux-media, devicetree, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 143 bytes --]
> https://lore.kernel.org/linux-arm-msm/20231010122539.1768825-1-bryan.odonoghue@linaro.org/
Sure, I'll revert it. Thanks for the heads up!
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 2/5] i2c: qcom-cci: Add sc8280xp compatible
2023-10-06 12:01 [PATCH 0/5] Add sc8280xp CCI and CAMSS core dtsi Bryan O'Donoghue
2023-10-06 12:01 ` [PATCH 1/5] dt-bindings: i2c: qcom-cci: Document sc8280xp compatible Bryan O'Donoghue
@ 2023-10-06 12:01 ` Bryan O'Donoghue
2023-10-06 23:21 ` Konrad Dybcio
2023-10-06 12:01 ` [PATCH 3/5] arm64: dts: qcom: sc8280xp: camss: Add CCI definitions Bryan O'Donoghue
` (2 subsequent siblings)
4 siblings, 1 reply; 20+ messages in thread
From: Bryan O'Donoghue @ 2023-10-06 12:01 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, loic.poulain, rfoss, andi.shyti,
robh+dt, krzysztof.kozlowski+dt, conor+dt, todor.too, mchehab,
bryan.odonoghue
Cc: linux-arm-msm, linux-i2c, linux-media, devicetree, linux-kernel
Add sc8280xp compatible with cci_v2_data parameters.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
drivers/i2c/busses/i2c-qcom-cci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/i2c/busses/i2c-qcom-cci.c b/drivers/i2c/busses/i2c-qcom-cci.c
index 414882c57d7f..677e4bc6e2c5 100644
--- a/drivers/i2c/busses/i2c-qcom-cci.c
+++ b/drivers/i2c/busses/i2c-qcom-cci.c
@@ -819,6 +819,7 @@ static const struct of_device_id cci_dt_match[] = {
{ .compatible = "qcom,msm8916-cci", .data = &cci_v1_data},
{ .compatible = "qcom,sdm845-cci", .data = &cci_v2_data},
{ .compatible = "qcom,sm8250-cci", .data = &cci_v2_data},
+ { .compatible = "qcom,sc8280xp-cci", .data = &cci_v2_data},
{ .compatible = "qcom,sm8450-cci", .data = &cci_v2_data},
{}
};
--
2.40.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH 2/5] i2c: qcom-cci: Add sc8280xp compatible
2023-10-06 12:01 ` [PATCH 2/5] i2c: qcom-cci: Add " Bryan O'Donoghue
@ 2023-10-06 23:21 ` Konrad Dybcio
2023-10-08 21:28 ` Andi Shyti
0 siblings, 1 reply; 20+ messages in thread
From: Konrad Dybcio @ 2023-10-06 23:21 UTC (permalink / raw)
To: Bryan O'Donoghue, agross, andersson, loic.poulain, rfoss,
andi.shyti, robh+dt, krzysztof.kozlowski+dt, conor+dt, todor.too,
mchehab
Cc: linux-arm-msm, linux-i2c, linux-media, devicetree, linux-kernel
On 6.10.2023 14:01, Bryan O'Donoghue wrote:
> Add sc8280xp compatible with cci_v2_data parameters.
>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> ---
Drop this patch, it adds nothing useful
Konrad
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 2/5] i2c: qcom-cci: Add sc8280xp compatible
2023-10-06 23:21 ` Konrad Dybcio
@ 2023-10-08 21:28 ` Andi Shyti
2023-10-08 22:13 ` Bryan O'Donoghue
2023-10-09 10:16 ` Konrad Dybcio
0 siblings, 2 replies; 20+ messages in thread
From: Andi Shyti @ 2023-10-08 21:28 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Bryan O'Donoghue, agross, andersson, loic.poulain, rfoss,
robh+dt, krzysztof.kozlowski+dt, conor+dt, todor.too, mchehab,
linux-arm-msm, linux-i2c, linux-media, devicetree, linux-kernel
Hi Konrad,
> > Add sc8280xp compatible with cci_v2_data parameters.
> >
> > Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> > ---
> Drop this patch, it adds nothing useful
what about the rest of the series?
Could you please be a bit more explicative?
Thanks,
Andi
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 2/5] i2c: qcom-cci: Add sc8280xp compatible
2023-10-08 21:28 ` Andi Shyti
@ 2023-10-08 22:13 ` Bryan O'Donoghue
2023-10-08 22:26 ` Bryan O'Donoghue
2023-10-09 10:16 ` Konrad Dybcio
1 sibling, 1 reply; 20+ messages in thread
From: Bryan O'Donoghue @ 2023-10-08 22:13 UTC (permalink / raw)
To: Andi Shyti, Konrad Dybcio
Cc: agross, andersson, loic.poulain, rfoss, robh+dt,
krzysztof.kozlowski+dt, conor+dt, todor.too, mchehab,
linux-arm-msm, linux-i2c, linux-media, devicetree, linux-kernel
On 08/10/2023 22:28, Andi Shyti wrote:
> Hi Konrad,
>
>>> Add sc8280xp compatible with cci_v2_data parameters.
>>>
>>> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
>>> ---
>> Drop this patch, it adds nothing useful
>
> what about the rest of the series?
>
> Could you please be a bit more explicative?
>
> Thanks,
> Andi
I think he means I can use the sm8250 or sm8450 compat string, which is
true.
---
bod
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 2/5] i2c: qcom-cci: Add sc8280xp compatible
2023-10-08 22:13 ` Bryan O'Donoghue
@ 2023-10-08 22:26 ` Bryan O'Donoghue
0 siblings, 0 replies; 20+ messages in thread
From: Bryan O'Donoghue @ 2023-10-08 22:26 UTC (permalink / raw)
To: Andi Shyti, Konrad Dybcio
Cc: agross, andersson, loic.poulain, rfoss, robh+dt,
krzysztof.kozlowski+dt, conor+dt, todor.too, mchehab,
linux-arm-msm, linux-i2c, linux-media, devicetree, linux-kernel
On 08/10/2023 23:13, Bryan O'Donoghue wrote:
> On 08/10/2023 22:28, Andi Shyti wrote:
>> Hi Konrad,
>>
>>>> Add sc8280xp compatible with cci_v2_data parameters.
>>>>
>>>> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
>>>> ---
>>> Drop this patch, it adds nothing useful
>>
>> what about the rest of the series?
>>
>> Could you please be a bit more explicative?
>>
>> Thanks,
>> Andi
>
> I think he means I can use the sm8250 or sm8450 compat string, which is
> true.
>
> ---
> bod
Tested, compat sm8250 works fine.
---
bod
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 2/5] i2c: qcom-cci: Add sc8280xp compatible
2023-10-08 21:28 ` Andi Shyti
2023-10-08 22:13 ` Bryan O'Donoghue
@ 2023-10-09 10:16 ` Konrad Dybcio
1 sibling, 0 replies; 20+ messages in thread
From: Konrad Dybcio @ 2023-10-09 10:16 UTC (permalink / raw)
To: Andi Shyti
Cc: Bryan O'Donoghue, agross, andersson, loic.poulain, rfoss,
robh+dt, krzysztof.kozlowski+dt, conor+dt, todor.too, mchehab,
linux-arm-msm, linux-i2c, linux-media, devicetree, linux-kernel
On 8.10.2023 23:28, Andi Shyti wrote:
> Hi Konrad,
>
>>> Add sc8280xp compatible with cci_v2_data parameters.
>>>
>>> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
>>> ---
>> Drop this patch, it adds nothing useful
>
> what about the rest of the series?
>
> Could you please be a bit more explicative?
This patch introduces a new compatible in the driver that does
exactly nothing, as the bindings require the use of
"qcom,sc8280xp-cci" with a fallback of "qcom,msm8996-cci". The
latter one already has a match table entry.
Konrad
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 3/5] arm64: dts: qcom: sc8280xp: camss: Add CCI definitions
2023-10-06 12:01 [PATCH 0/5] Add sc8280xp CCI and CAMSS core dtsi Bryan O'Donoghue
2023-10-06 12:01 ` [PATCH 1/5] dt-bindings: i2c: qcom-cci: Document sc8280xp compatible Bryan O'Donoghue
2023-10-06 12:01 ` [PATCH 2/5] i2c: qcom-cci: Add " Bryan O'Donoghue
@ 2023-10-06 12:01 ` Bryan O'Donoghue
2023-10-06 12:01 ` [PATCH 4/5] media: dt-bindings: media: camss: Add qcom,sc8280xp-camss binding Bryan O'Donoghue
2023-10-06 12:01 ` [PATCH 5/5] arm64: dts: qcom: sc8280xp: camss: Add CAMSS block definition Bryan O'Donoghue
4 siblings, 0 replies; 20+ messages in thread
From: Bryan O'Donoghue @ 2023-10-06 12:01 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, loic.poulain, rfoss, andi.shyti,
robh+dt, krzysztof.kozlowski+dt, conor+dt, todor.too, mchehab,
bryan.odonoghue
Cc: linux-arm-msm, linux-i2c, linux-media, devicetree, linux-kernel
sc8280xp has four Camera Control Interface (CCI) blocks which pinout to
two I2C master controllers for each CCI.
The CCI I2C pins are not muxed so we define them in the dtsi.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 324 +++++++++++++++++++++++++
1 file changed, 324 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index fafea0f34fd9..199b112da295 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -3451,6 +3451,170 @@ usb_1_role_switch: endpoint {
};
};
+ cci0: cci@ac4a000 {
+ compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0 0x0ac4a000 0 0x1000>;
+ interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc TITAN_TOP_GDSC>;
+
+ clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
+ <&camcc CAMCC_SLOW_AHB_CLK_SRC>,
+ <&camcc CAMCC_CPAS_AHB_CLK>,
+ <&camcc CAMCC_CCI_0_CLK>,
+ <&camcc CAMCC_CCI_0_CLK_SRC>;
+ clock-names = "camnoc_axi",
+ "slow_ahb_src",
+ "cpas_ahb",
+ "cci",
+ "cci_src";
+
+ pinctrl-0 = <&cci0_default>;
+ pinctrl-1 = <&cci0_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ status = "disabled";
+
+ cci0_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci0_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cci1: cci@ac4b000 {
+ compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0 0x0ac4b000 0 0x1000>;
+ interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc TITAN_TOP_GDSC>;
+
+ clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
+ <&camcc CAMCC_SLOW_AHB_CLK_SRC>,
+ <&camcc CAMCC_CPAS_AHB_CLK>,
+ <&camcc CAMCC_CCI_1_CLK>,
+ <&camcc CAMCC_CCI_1_CLK_SRC>;
+ clock-names = "camnoc_axi",
+ "slow_ahb_src",
+ "cpas_ahb",
+ "cci",
+ "cci_src";
+
+ pinctrl-0 = <&cci1_default>;
+ pinctrl-1 = <&cci1_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ status = "disabled";
+
+ cci1_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci1_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cci2: cci@ac4c000 {
+ compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0 0x0ac4c000 0 0x1000>;
+ interrupts = <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc TITAN_TOP_GDSC>;
+
+ clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
+ <&camcc CAMCC_SLOW_AHB_CLK_SRC>,
+ <&camcc CAMCC_CPAS_AHB_CLK>,
+ <&camcc CAMCC_CCI_2_CLK>,
+ <&camcc CAMCC_CCI_2_CLK_SRC>;
+ clock-names = "camnoc_axi",
+ "slow_ahb_src",
+ "cpas_ahb",
+ "cci",
+ "cci_src";
+
+ pinctrl-0 = <&cci2_default>;
+ pinctrl-1 = <&cci2_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ status = "disabled";
+
+ cci2_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci2_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cci3: cci@ac4d000 {
+ compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0 0x0ac4d000 0 0x1000>;
+ interrupts = <GIC_SPI 650 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc TITAN_TOP_GDSC>;
+
+ clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
+ <&camcc CAMCC_SLOW_AHB_CLK_SRC>,
+ <&camcc CAMCC_CPAS_AHB_CLK>,
+ <&camcc CAMCC_CCI_3_CLK>,
+ <&camcc CAMCC_CCI_3_CLK_SRC>;
+ clock-names = "camnoc_axi",
+ "slow_ahb_src",
+ "cpas_ahb",
+ "cci",
+ "cci_src";
+
+ pinctrl-0 = <&cci3_default>;
+ pinctrl-1 = <&cci3_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ status = "disabled";
+
+ cci3_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci3_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
camcc: clock-controller@ad00000 {
compatible = "qcom,sc8280xp-camcc";
reg = <0 0x0ad00000 0 0x20000>;
@@ -4075,6 +4239,166 @@ tlmm: pinctrl@f100000 {
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 230>;
wakeup-parent = <&pdc>;
+
+ cci0_default: cci0-default-state {
+ cci0_i2c0_default: cci0-i2c0-default-pins {
+ /* cci_i2c_sda0, cci_i2c_scl0 */
+ pins = "gpio113", "gpio114";
+ function = "cci_i2c";
+
+ bias-pull-up;
+ drive-strength = <2>; /* 2 mA */
+ };
+
+ cci0_i2c1_default: cci0-i2c1-default-pins {
+ /* cci_i2c_sda1, cci_i2c_scl1 */
+ pins = "gpio115", "gpio116";
+ function = "cci_i2c";
+
+ bias-pull-up;
+ drive-strength = <2>; /* 2 mA */
+ };
+ };
+
+ cci0_sleep: cci0-sleep-state {
+ cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
+ /* cci_i2c_sda0, cci_i2c_scl0 */
+ pins = "gpio113", "gpio114";
+ function = "cci_i2c";
+
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down;
+ };
+
+ cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
+ /* cci_i2c_sda1, cci_i2c_scl1 */
+ pins = "gpio115", "gpio116";
+ function = "cci_i2c";
+
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down;
+ };
+ };
+
+ cci1_default: cci1-default-state {
+ cci1_i2c0_default: cci1-i2c0-default-pins {
+ /* cci_i2c_sda2, cci_i2c_scl2 */
+ pins = "gpio10","gpio11";
+ function = "cci_i2c";
+
+ bias-pull-up;
+ drive-strength = <2>; /* 2 mA */
+ };
+
+ cci1_i2c1_default: cci1-i2c1-default-pins {
+ /* cci_i2c_sda3, cci_i2c_scl3 */
+ pins = "gpio123","gpio124";
+ function = "cci_i2c";
+
+ bias-pull-up;
+ drive-strength = <2>; /* 2 mA */
+ };
+ };
+
+ cci1_sleep: cci1-sleep-state {
+ cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
+ /* cci_i2c_sda2, cci_i2c_scl2 */
+ pins = "gpio10","gpio11";
+ function = "cci_i2c";
+
+ bias-pull-down;
+ drive-strength = <2>; /* 2 mA */
+ };
+
+ cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
+ /* cci_i2c_sda3, cci_i2c_scl3 */
+ pins = "gpio123","gpio124";
+ function = "cci_i2c";
+
+ bias-pull-down;
+ drive-strength = <2>; /* 2 mA */
+ };
+ };
+
+ cci2_default: cci2-default-state {
+ cci2_i2c0_default: cci2-i2c0-default-pins {
+ /* cci_i2c_sda4, cci_i2c_scl4 */
+ pins = "gpio117","gpio118";
+ function = "cci_i2c";
+
+ bias-pull-up;
+ drive-strength = <2>; /* 2 mA */
+ };
+
+ cci2_i2c1_default: cci2-i2c1-default-pins {
+ /* cci_i2c_sda5, cci_i2c_scl5 */
+ pins = "gpio12","gpio13";
+ function = "cci_i2c";
+
+ bias-pull-up;
+ drive-strength = <2>; /* 2 mA */
+ };
+ };
+
+ cci2_sleep: cci2-sleep-state {
+ cci2_i2c0_sleep: cci2-i2c0-sleep-pins {
+ /* cci_i2c_sda4, cci_i2c_scl4 */
+ pins = "gpio117","gpio118";
+ function = "cci_i2c";
+
+ bias-pull-down;
+ drive-strength = <2>; /* 2 mA */
+ };
+
+ cci2_i2c1_sleep: cci2-i2c1-sleep-pins {
+ /* cci_i2c_sda5, cci_i2c_scl5 */
+ pins = "gpio12","gpio13";
+ function = "cci_i2c";
+
+ bias-pull-down;
+ drive-strength = <2>; /* 2 mA */
+ };
+ };
+
+ cci3_default: cci3-default-state {
+ cci3_i2c0_default: cci3-i2c0-default-pins {
+ /* cci_i2c_sda6, cci_i2c_scl6 */
+ pins = "gpio145","gpio146";
+ function = "cci_i2c";
+
+ bias-pull-up;
+ drive-strength = <2>; /* 2 mA */
+ };
+
+ cci3_i2c1_default: cci3-i2c1-default-pins {
+ /* cci_i2c_sda7, cci_i2c_scl7 */
+ pins = "gpio164","gpio165";
+ function = "cci_i2c";
+
+ bias-pull-up;
+ drive-strength = <2>; /* 2 mA */
+ };
+ };
+
+ cci3_sleep: cci3-sleep-state {
+ cci3_i2c0_sleep: cci3-i2c0-sleep-pins {
+ /* cci_i2c_sda6, cci_i2c_scl6 */
+ pins = "gpio145","gpio146";
+ function = "cci_i2c";
+
+ bias-pull-down;
+ drive-strength = <2>; /* 2 mA */
+ };
+
+ cci3_i2c1_sleep: cci3-i2c1-sleep-pins {
+ /* cci_i2c_sda7, cci_i2c_scl7 */
+ pins = "gpio164","gpio165";
+ function = "cci_i2c";
+
+ bias-pull-down;
+ drive-strength = <2>; /* 2 mA */
+ };
+ };
};
apps_smmu: iommu@15000000 {
--
2.40.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 4/5] media: dt-bindings: media: camss: Add qcom,sc8280xp-camss binding
2023-10-06 12:01 [PATCH 0/5] Add sc8280xp CCI and CAMSS core dtsi Bryan O'Donoghue
` (2 preceding siblings ...)
2023-10-06 12:01 ` [PATCH 3/5] arm64: dts: qcom: sc8280xp: camss: Add CCI definitions Bryan O'Donoghue
@ 2023-10-06 12:01 ` Bryan O'Donoghue
2023-10-06 12:33 ` Krzysztof Kozlowski
2023-10-06 13:58 ` Rob Herring
2023-10-06 12:01 ` [PATCH 5/5] arm64: dts: qcom: sc8280xp: camss: Add CAMSS block definition Bryan O'Donoghue
4 siblings, 2 replies; 20+ messages in thread
From: Bryan O'Donoghue @ 2023-10-06 12:01 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, loic.poulain, rfoss, andi.shyti,
robh+dt, krzysztof.kozlowski+dt, conor+dt, todor.too, mchehab,
bryan.odonoghue
Cc: linux-arm-msm, linux-i2c, linux-media, devicetree, linux-kernel
Add bindings for qcom,sc8280xp-camss in order to support the camera
subsystem for sc8280xp as found in the Lenovo x13s Laptop.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
.../bindings/media/qcom,sc8280xp-camss.yaml | 598 ++++++++++++++++++
1 file changed, 598 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.yaml
diff --git a/Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.yaml
new file mode 100644
index 000000000000..46d2da4ad373
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.yaml
@@ -0,0 +1,598 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,sc8280xp-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm CAMSS
+
+maintainers:
+ - Bryan O'Donoghue <bryan.odonoghue@linaro.org>
+
+description: |
+ The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
+
+properties:
+ compatible:
+ const: qcom,sc8280xp-camss
+
+ clocks:
+ minItems: 63
+ maxItems: 63
+
+ clock-names:
+ items:
+ - const: camnoc_axi
+ - const: camnoc_axi_src
+ - const: cpas_ahb
+ - const: cphy_rx_src
+ - const: csiphy0
+ - const: csiphy0_timer_src
+ - const: csiphy0_timer
+ - const: csiphy1
+ - const: csiphy1_timer_src
+ - const: csiphy1_timer
+ - const: csiphy2
+ - const: csiphy2_timer_src
+ - const: csiphy2_timer
+ - const: csiphy3
+ - const: csiphy3_timer_src
+ - const: csiphy3_timer
+ - const: vfe0_axi
+ - const: vfe0_src
+ - const: vfe0
+ - const: vfe0_cphy_rx
+ - const: vfe0_csid_src
+ - const: vfe0_csid
+ - const: vfe1_axi
+ - const: vfe1_src
+ - const: vfe1
+ - const: vfe1_cphy_rx
+ - const: vfe1_csid_src
+ - const: vfe1_csid
+ - const: vfe2_axi
+ - const: vfe2_src
+ - const: vfe2
+ - const: vfe2_cphy_rx
+ - const: vfe2_csid_src
+ - const: vfe2_csid
+ - const: vfe3_axi
+ - const: vfe3_src
+ - const: vfe3
+ - const: vfe3_cphy_rx
+ - const: vfe3_csid_src
+ - const: vfe3_csid
+ - const: vfe_lite0_src
+ - const: vfe_lite0
+ - const: vfe_lite0_cphy_rx
+ - const: vfe_lite0_csid_src
+ - const: vfe_lite0_csid
+ - const: vfe_lite1_src
+ - const: vfe_lite1
+ - const: vfe_lite1_cphy_rx
+ - const: vfe_lite1_csid_src
+ - const: vfe_lite1_csid
+ - const: vfe_lite2_src
+ - const: vfe_lite2
+ - const: vfe_lite2_cphy_rx
+ - const: vfe_lite2_csid_src
+ - const: vfe_lite2_csid
+ - const: vfe_lite3_src
+ - const: vfe_lite3
+ - const: vfe_lite3_cphy_rx
+ - const: vfe_lite3_csid_src
+ - const: vfe_lite3_csid
+ - const: gcc_axi_hf
+ - const: gcc_axi_sf
+ - const: slow_ahb_src
+
+ interrupts:
+ minItems: 20
+ maxItems: 20
+
+ interrupt-names:
+ items:
+ - const: csid1_lite
+ - const: vfe_lite1
+ - const: csiphy3
+ - const: csid0
+ - const: vfe0
+ - const: csid1
+ - const: vfe1
+ - const: csid0_lite
+ - const: vfe_lite0
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: csid2
+ - const: vfe2
+ - const: csid3_lite
+ - const: csid2_lite
+ - const: vfe_lite3
+ - const: vfe_lite2
+ - const: csid3
+ - const: vfe3
+
+ iommus:
+ minItems: 16
+ maxItems: 16
+
+ interconnects:
+ minItems: 4
+ maxItems: 4
+
+ interconnect-names:
+ items:
+ - const: cam_ahb
+ - const: cam_hf_mnoc
+ - const: cam_sf_mnoc
+ - const: cam_sf_icp_mnoc
+
+ power-domains:
+ items:
+ - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
+ - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
+ - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller.
+ - description: IFE3 GDSC - Image Front End, Global Distributed Switch Controller.
+ - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller.
+
+ power-domain-names:
+ items:
+ - description: ife0
+ - description: ife1
+ - description: ife2
+ - description: ife3
+ - description: top
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ description:
+ CSI input ports.
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ maxItems: 1
+
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - clock-lanes
+ - data-lanes
+
+ port@1:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ maxItems: 1
+
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - clock-lanes
+ - data-lanes
+
+ port@2:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ maxItems: 1
+
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - clock-lanes
+ - data-lanes
+
+ port@3:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ maxItems: 1
+
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - clock-lanes
+ - data-lanes
+
+ reg:
+ minItems: 20
+ maxItems: 20
+
+ reg-names:
+ items:
+ - const: csiphy2
+ - const: csiphy3
+ - const: csiphy0
+ - const: csiphy1
+ - const: vfe0
+ - const: csid0
+ - const: vfe1
+ - const: csid1
+ - const: vfe2
+ - const: csid2
+ - const: vfe_lite0
+ - const: csid0_lite
+ - const: vfe_lite1
+ - const: csid1_lite
+ - const: vfe_lite2
+ - const: csid2_lite
+ - const: vfe_lite3
+ - const: csid3_lite
+ - const: vfe3
+ - const: csid3
+
+ vdda-phy-supply:
+ description:
+ Phandle to a regulator supply to PHY core block.
+
+ vdda-pll-supply:
+ description:
+ Phandle to 1.8V regulator supply to PHY refclk pll block.
+
+required:
+ - clock-names
+ - clocks
+ - compatible
+ - interconnects
+ - interconnect-names
+ - interrupts
+ - interrupt-names
+ - iommus
+ - power-domains
+ - power-domain-names
+ - reg
+ - reg-names
+ - vdda-phy-supply
+ - vdda-pll-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
+ #include <dt-bindings/clock/qcom,sc8280xp-camcc.h>
+ #include <dt-bindings/interconnect/qcom,sc8280xp.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ camss: camss@ac5a000 {
+ compatible = "qcom,sc8280xp-camss";
+
+ reg = <0 0x0ac5a000 0 0x2000>,
+ <0 0x0ac5c000 0 0x2000>,
+ <0 0x0ac65000 0 0x2000>,
+ <0 0x0ac67000 0 0x2000>,
+ <0 0x0acaf000 0 0x4000>,
+ <0 0x0acb3000 0 0x1000>,
+ <0 0x0acb6000 0 0x4000>,
+ <0 0x0acba000 0 0x1000>,
+ <0 0x0acbd000 0 0x4000>,
+ <0 0x0acc1000 0 0x1000>,
+ <0 0x0acc4000 0 0x4000>,
+ <0 0x0acc8000 0 0x1000>,
+ <0 0x0accb000 0 0x4000>,
+ <0 0x0accf000 0 0x1000>,
+ <0 0x0acd2000 0 0x4000>,
+ <0 0x0acd6000 0 0x1000>,
+ <0 0x0acd9000 0 0x4000>,
+ <0 0x0acdd000 0 0x1000>,
+ <0 0x0ace0000 0 0x4000>,
+ <0 0x0ace4000 0 0x1000>;
+
+ reg-names = "csiphy2",
+ "csiphy3",
+ "csiphy0",
+ "csiphy1",
+ "vfe0",
+ "csid0",
+ "vfe1",
+ "csid1",
+ "vfe2",
+ "csid2",
+ "vfe_lite0",
+ "csid0_lite",
+ "vfe_lite1",
+ "csid1_lite",
+ "vfe_lite2",
+ "csid2_lite",
+ "vfe_lite3",
+ "csid3_lite",
+ "vfe3",
+ "csid3";
+
+ vdda-phy-supply = <&vreg_l6d>;
+ vdda-pll-supply = <&vreg_l4d>;
+
+ interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-names = "csid1_lite",
+ "vfe_lite1",
+ "csiphy3",
+ "csid0",
+ "vfe0",
+ "csid1",
+ "vfe1",
+ "csid0_lite",
+ "vfe_lite0",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csid2",
+ "vfe2",
+ "csid3_lite",
+ "csid2_lite",
+ "vfe_lite3",
+ "vfe_lite2",
+ "csid3",
+ "vfe3";
+
+ power-domains = <&camcc IFE_0_GDSC>,
+ <&camcc IFE_1_GDSC>,
+ <&camcc IFE_2_GDSC>,
+ <&camcc IFE_3_GDSC>,
+ <&camcc TITAN_TOP_GDSC>;
+
+ power-domain-names = "ife0",
+ "ife1",
+ "ife2",
+ "ife3",
+ "top";
+
+ clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
+ <&camcc CAMCC_CAMNOC_AXI_CLK_SRC>,
+ <&camcc CAMCC_CPAS_AHB_CLK>,
+ <&camcc CAMCC_CPHY_RX_CLK_SRC>,
+ <&camcc CAMCC_CSIPHY0_CLK>,
+ <&camcc CAMCC_CSI0PHYTIMER_CLK_SRC>,
+ <&camcc CAMCC_CSI0PHYTIMER_CLK>,
+ <&camcc CAMCC_CSIPHY1_CLK>,
+ <&camcc CAMCC_CSI1PHYTIMER_CLK_SRC>,
+ <&camcc CAMCC_CSI1PHYTIMER_CLK>,
+ <&camcc CAMCC_CSIPHY2_CLK>,
+ <&camcc CAMCC_CSI2PHYTIMER_CLK_SRC>,
+ <&camcc CAMCC_CSI2PHYTIMER_CLK>,
+ <&camcc CAMCC_CSIPHY3_CLK>,
+ <&camcc CAMCC_CSI3PHYTIMER_CLK_SRC>,
+ <&camcc CAMCC_CSI3PHYTIMER_CLK>,
+ <&camcc CAMCC_IFE_0_AXI_CLK>,
+ <&camcc CAMCC_IFE_0_CLK_SRC>,
+ <&camcc CAMCC_IFE_0_CLK>,
+ <&camcc CAMCC_IFE_0_CPHY_RX_CLK>,
+ <&camcc CAMCC_IFE_0_CSID_CLK_SRC>,
+ <&camcc CAMCC_IFE_0_CSID_CLK>,
+ <&camcc CAMCC_IFE_1_AXI_CLK>,
+ <&camcc CAMCC_IFE_1_CLK_SRC>,
+ <&camcc CAMCC_IFE_1_CLK>,
+ <&camcc CAMCC_IFE_1_CPHY_RX_CLK>,
+ <&camcc CAMCC_IFE_1_CSID_CLK_SRC>,
+ <&camcc CAMCC_IFE_1_CSID_CLK>,
+ <&camcc CAMCC_IFE_2_AXI_CLK>,
+ <&camcc CAMCC_IFE_2_CLK_SRC>,
+ <&camcc CAMCC_IFE_2_CLK>,
+ <&camcc CAMCC_IFE_2_CPHY_RX_CLK>,
+ <&camcc CAMCC_IFE_2_CSID_CLK_SRC>,
+ <&camcc CAMCC_IFE_2_CSID_CLK>,
+ <&camcc CAMCC_IFE_3_AXI_CLK>,
+ <&camcc CAMCC_IFE_3_CLK_SRC>,
+ <&camcc CAMCC_IFE_3_CLK>,
+ <&camcc CAMCC_IFE_3_CPHY_RX_CLK>,
+ <&camcc CAMCC_IFE_3_CSID_CLK_SRC>,
+ <&camcc CAMCC_IFE_3_CSID_CLK>,
+ <&camcc CAMCC_IFE_LITE_0_CLK_SRC>,
+ <&camcc CAMCC_IFE_LITE_0_CLK>,
+ <&camcc CAMCC_IFE_LITE_0_CPHY_RX_CLK>,
+ <&camcc CAMCC_IFE_LITE_0_CSID_CLK_SRC>,
+ <&camcc CAMCC_IFE_LITE_0_CSID_CLK>,
+ <&camcc CAMCC_IFE_LITE_1_CLK_SRC>,
+ <&camcc CAMCC_IFE_LITE_1_CLK>,
+ <&camcc CAMCC_IFE_LITE_1_CPHY_RX_CLK>,
+ <&camcc CAMCC_IFE_LITE_1_CSID_CLK_SRC>,
+ <&camcc CAMCC_IFE_LITE_1_CSID_CLK>,
+ <&camcc CAMCC_IFE_LITE_2_CLK_SRC>,
+ <&camcc CAMCC_IFE_LITE_2_CLK>,
+ <&camcc CAMCC_IFE_LITE_2_CPHY_RX_CLK>,
+ <&camcc CAMCC_IFE_LITE_2_CSID_CLK_SRC>,
+ <&camcc CAMCC_IFE_LITE_2_CSID_CLK>,
+ <&camcc CAMCC_IFE_LITE_3_CLK_SRC>,
+ <&camcc CAMCC_IFE_LITE_3_CLK>,
+ <&camcc CAMCC_IFE_LITE_3_CPHY_RX_CLK>,
+ <&camcc CAMCC_IFE_LITE_3_CSID_CLK_SRC>,
+ <&camcc CAMCC_IFE_LITE_3_CSID_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&gcc GCC_CAMERA_SF_AXI_CLK>,
+ <&camcc CAMCC_SLOW_AHB_CLK_SRC>;
+
+ clock-names = "camnoc_axi",
+ "camnoc_axi_src",
+ "cpas_ahb",
+ "cphy_rx_src",
+ "csiphy0",
+ "csiphy0_timer_src",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer_src",
+ "csiphy1_timer",
+ "csiphy2",
+ "csiphy2_timer_src",
+ "csiphy2_timer",
+ "csiphy3",
+ "csiphy3_timer_src",
+ "csiphy3_timer",
+ "vfe0_axi",
+ "vfe0_src",
+ "vfe0",
+ "vfe0_cphy_rx",
+ "vfe0_csid_src",
+ "vfe0_csid",
+ "vfe1_axi",
+ "vfe1_src",
+ "vfe1",
+ "vfe1_cphy_rx",
+ "vfe1_csid_src",
+ "vfe1_csid",
+ "vfe2_axi",
+ "vfe2_src",
+ "vfe2",
+ "vfe2_cphy_rx",
+ "vfe2_csid_src",
+ "vfe2_csid",
+ "vfe3_axi",
+ "vfe3_src",
+ "vfe3",
+ "vfe3_cphy_rx",
+ "vfe3_csid_src",
+ "vfe3_csid",
+ "vfe_lite0_src",
+ "vfe_lite0",
+ "vfe_lite0_cphy_rx",
+ "vfe_lite0_csid_src",
+ "vfe_lite0_csid",
+ "vfe_lite1_src",
+ "vfe_lite1",
+ "vfe_lite1_cphy_rx",
+ "vfe_lite1_csid_src",
+ "vfe_lite1_csid",
+ "vfe_lite2_src",
+ "vfe_lite2",
+ "vfe_lite2_cphy_rx",
+ "vfe_lite2_csid_src",
+ "vfe_lite2_csid",
+ "vfe_lite3_src",
+ "vfe_lite3",
+ "vfe_lite3_cphy_rx",
+ "vfe_lite3_csid_src",
+ "vfe_lite3_csid",
+ "gcc_axi_hf",
+ "gcc_axi_sf",
+ "slow_ahb_src";
+
+
+ iommus = <&apps_smmu 0x2000 0x4e0>,
+ <&apps_smmu 0x2020 0x4e0>,
+ <&apps_smmu 0x2040 0x4e0>,
+ <&apps_smmu 0x2060 0x4e0>,
+ <&apps_smmu 0x2080 0x4e0>,
+ <&apps_smmu 0x20e0 0x4e0>,
+ <&apps_smmu 0x20c0 0x4e0>,
+ <&apps_smmu 0x20a0 0x4e0>,
+ <&apps_smmu 0x2400 0x4e0>,
+ <&apps_smmu 0x2420 0x4e0>,
+ <&apps_smmu 0x2440 0x4e0>,
+ <&apps_smmu 0x2460 0x4e0>,
+ <&apps_smmu 0x2480 0x4e0>,
+ <&apps_smmu 0x24e0 0x4e0>,
+ <&apps_smmu 0x24c0 0x4e0>,
+ <&apps_smmu 0x24a0 0x4e0>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>,
+ <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>,
+ <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>,
+ <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "cam_ahb",
+ "cam_hf_mnoc",
+ "cam_sf_mnoc",
+ "cam_sf_icp_mnoc";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ port@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ port@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
+ };
--
2.40.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH 4/5] media: dt-bindings: media: camss: Add qcom,sc8280xp-camss binding
2023-10-06 12:01 ` [PATCH 4/5] media: dt-bindings: media: camss: Add qcom,sc8280xp-camss binding Bryan O'Donoghue
@ 2023-10-06 12:33 ` Krzysztof Kozlowski
2023-10-06 12:52 ` Bryan O'Donoghue
2023-10-06 15:12 ` Rob Herring
2023-10-06 13:58 ` Rob Herring
1 sibling, 2 replies; 20+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-06 12:33 UTC (permalink / raw)
To: Bryan O'Donoghue, agross, andersson, konrad.dybcio,
loic.poulain, rfoss, andi.shyti, robh+dt, krzysztof.kozlowski+dt,
conor+dt, todor.too, mchehab
Cc: linux-arm-msm, linux-i2c, linux-media, devicetree, linux-kernel
On 06/10/2023 14:01, Bryan O'Donoghue wrote:
> Add bindings for qcom,sc8280xp-camss in order to support the camera
> subsystem for sc8280xp as found in the Lenovo x13s Laptop.
>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> ---
> .../bindings/media/qcom,sc8280xp-camss.yaml | 598 ++++++++++++++++++
> 1 file changed, 598 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.yaml
>
> diff --git a/Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.yaml
> new file mode 100644
> index 000000000000..46d2da4ad373
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.yaml
> @@ -0,0 +1,598 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/qcom,sc8280xp-camss.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm CAMSS
Instead something like:
Qualcomm SC8280xp Camera SubSystem (CAMSS)
?
> +
> +maintainers:
> + - Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> +
> +description: |
> + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
> +
> +properties:
> + compatible:
> + const: qcom,sc8280xp-camss
> +
> + clocks:
> + minItems: 63
You can drop minItems if they equal maxItems.
> + maxItems: 63
> +
> + clock-names:
> + items:
> + - const: camnoc_axi
> + - const: camnoc_axi_src
> + - const: cpas_ahb
> + - const: cphy_rx_src
> + - const: csiphy0
> + - const: csiphy0_timer_src
> + - const: csiphy0_timer
> + - const: csiphy1
> + - const: csiphy1_timer_src
> + - const: csiphy1_timer
> + - const: csiphy2
> + - const: csiphy2_timer_src
> + - const: csiphy2_timer
> + - const: csiphy3
> + - const: csiphy3_timer_src
> + - const: csiphy3_timer
> + - const: vfe0_axi
> + - const: vfe0_src
> + - const: vfe0
> + - const: vfe0_cphy_rx
> + - const: vfe0_csid_src
> + - const: vfe0_csid
> + - const: vfe1_axi
> + - const: vfe1_src
> + - const: vfe1
> + - const: vfe1_cphy_rx
> + - const: vfe1_csid_src
> + - const: vfe1_csid
> + - const: vfe2_axi
> + - const: vfe2_src
> + - const: vfe2
> + - const: vfe2_cphy_rx
> + - const: vfe2_csid_src
> + - const: vfe2_csid
> + - const: vfe3_axi
> + - const: vfe3_src
> + - const: vfe3
> + - const: vfe3_cphy_rx
> + - const: vfe3_csid_src
> + - const: vfe3_csid
> + - const: vfe_lite0_src
> + - const: vfe_lite0
> + - const: vfe_lite0_cphy_rx
> + - const: vfe_lite0_csid_src
> + - const: vfe_lite0_csid
> + - const: vfe_lite1_src
> + - const: vfe_lite1
> + - const: vfe_lite1_cphy_rx
> + - const: vfe_lite1_csid_src
> + - const: vfe_lite1_csid
> + - const: vfe_lite2_src
> + - const: vfe_lite2
> + - const: vfe_lite2_cphy_rx
> + - const: vfe_lite2_csid_src
> + - const: vfe_lite2_csid
> + - const: vfe_lite3_src
> + - const: vfe_lite3
> + - const: vfe_lite3_cphy_rx
> + - const: vfe_lite3_csid_src
> + - const: vfe_lite3_csid
> + - const: gcc_axi_hf
> + - const: gcc_axi_sf
> + - const: slow_ahb_src
> +
> + interrupts:
> + minItems: 20
You can drop minItems if they equal maxItems.
> + maxItems: 20
> +
> + interrupt-names:
> + items:
> + - const: csid1_lite
> + - const: vfe_lite1
> + - const: csiphy3
> + - const: csid0
> + - const: vfe0
> + - const: csid1
> + - const: vfe1
> + - const: csid0_lite
> + - const: vfe_lite0
> + - const: csiphy0
> + - const: csiphy1
> + - const: csiphy2
> + - const: csid2
> + - const: vfe2
> + - const: csid3_lite
> + - const: csid2_lite
> + - const: vfe_lite3
> + - const: vfe_lite2
> + - const: csid3
> + - const: vfe3
> +
> + iommus:
> + minItems: 16
You can drop minItems if they equal maxItems.
> + maxItems: 16
> +
> + interconnects:
> + minItems: 4
You can drop minItems if they equal maxItems.
> + maxItems: 4
> +
> + interconnect-names:
> + items:
> + - const: cam_ahb
> + - const: cam_hf_mnoc
> + - const: cam_sf_mnoc
> + - const: cam_sf_icp_mnoc
> +
> + power-domains:
> + items:
> + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
> + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
> + - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller.
> + - description: IFE3 GDSC - Image Front End, Global Distributed Switch Controller.
> + - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller.
> +
> + power-domain-names:
> + items:
> + - description: ife0
> + - description: ife1
> + - description: ife2
> + - description: ife3
> + - description: top
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
On this level of indentation:
additionalProperties: false
> + description:
> + CSI input ports.
> +
> + properties:
> + port@0:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description:
> + Input port for receiving CSI data.
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + clock-lanes:
> + maxItems: 1
> +
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + required:
> + - clock-lanes
> + - data-lanes
> +
> + port@1:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description:
> + Input port for receiving CSI data.
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + clock-lanes:
> + maxItems: 1
> +
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + required:
> + - clock-lanes
> + - data-lanes
> +
> + port@2:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description:
> + Input port for receiving CSI data.
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + clock-lanes:
> + maxItems: 1
> +
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + required:
> + - clock-lanes
> + - data-lanes
> +
> + port@3:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description:
> + Input port for receiving CSI data.
No output ports to some ISP?
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + clock-lanes:
> + maxItems: 1
> +
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + required:
> + - clock-lanes
> + - data-lanes
> +
> + reg:
> + minItems: 20
Drop
> + maxItems: 20
> +
> + reg-names:
> + items:
> + - const: csiphy2
> + - const: csiphy3
> + - const: csiphy0
> + - const: csiphy1
> + - const: vfe0
> + - const: csid0
> + - const: vfe1
> + - const: csid1
> + - const: vfe2
> + - const: csid2
> + - const: vfe_lite0
> + - const: csid0_lite
> + - const: vfe_lite1
> + - const: csid1_lite
> + - const: vfe_lite2
> + - const: csid2_lite
> + - const: vfe_lite3
> + - const: csid3_lite
> + - const: vfe3
> + - const: csid3
> +
> + vdda-phy-supply:
> + description:
> + Phandle to a regulator supply to PHY core block.
> +
> + vdda-pll-supply:
> + description:
> + Phandle to 1.8V regulator supply to PHY refclk pll block.
> +
> +required:
> + - clock-names
> + - clocks
> + - compatible
> + - interconnects
> + - interconnect-names
> + - interrupts
> + - interrupt-names
> + - iommus
> + - power-domains
> + - power-domain-names
> + - reg
> + - reg-names
> + - vdda-phy-supply
> + - vdda-pll-supply
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
> + #include <dt-bindings/clock/qcom,sc8280xp-camcc.h>
> + #include <dt-bindings/interconnect/qcom,sc8280xp.h>
> + #include <dt-bindings/power/qcom-rpmpd.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + camss: camss@ac5a000 {
> + compatible = "qcom,sc8280xp-camss";
> +
> + reg = <0 0x0ac5a000 0 0x2000>,
> + <0 0x0ac5c000 0 0x2000>,
> + <0 0x0ac65000 0 0x2000>,
> + <0 0x0ac67000 0 0x2000>,
> + <0 0x0acaf000 0 0x4000>,
> + <0 0x0acb3000 0 0x1000>,
> + <0 0x0acb6000 0 0x4000>,
> + <0 0x0acba000 0 0x1000>,
> + <0 0x0acbd000 0 0x4000>,
> + <0 0x0acc1000 0 0x1000>,
> + <0 0x0acc4000 0 0x4000>,
> + <0 0x0acc8000 0 0x1000>,
> + <0 0x0accb000 0 0x4000>,
> + <0 0x0accf000 0 0x1000>,
> + <0 0x0acd2000 0 0x4000>,
> + <0 0x0acd6000 0 0x1000>,
> + <0 0x0acd9000 0 0x4000>,
> + <0 0x0acdd000 0 0x1000>,
> + <0 0x0ace0000 0 0x4000>,
> + <0 0x0ace4000 0 0x1000>;
> +
> + reg-names = "csiphy2",
> + "csiphy3",
> + "csiphy0",
> + "csiphy1",
> + "vfe0",
> + "csid0",
> + "vfe1",
> + "csid1",
> + "vfe2",
> + "csid2",
> + "vfe_lite0",
> + "csid0_lite",
> + "vfe_lite1",
> + "csid1_lite",
> + "vfe_lite2",
> + "csid2_lite",
> + "vfe_lite3",
> + "csid3_lite",
> + "vfe3",
> + "csid3";
> +
> + vdda-phy-supply = <&vreg_l6d>;
> + vdda-pll-supply = <&vreg_l4d>;
> +
> + interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>;
> +
> + interrupt-names = "csid1_lite",
> + "vfe_lite1",
> + "csiphy3",
> + "csid0",
> + "vfe0",
> + "csid1",
> + "vfe1",
> + "csid0_lite",
> + "vfe_lite0",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "csid2",
> + "vfe2",
> + "csid3_lite",
> + "csid2_lite",
> + "vfe_lite3",
> + "vfe_lite2",
> + "csid3",
> + "vfe3";
> +
> + power-domains = <&camcc IFE_0_GDSC>,
> + <&camcc IFE_1_GDSC>,
> + <&camcc IFE_2_GDSC>,
> + <&camcc IFE_3_GDSC>,
> + <&camcc TITAN_TOP_GDSC>;
> +
> + power-domain-names = "ife0",
> + "ife1",
> + "ife2",
> + "ife3",
> + "top";
> +
> + clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
> + <&camcc CAMCC_CAMNOC_AXI_CLK_SRC>,
> + <&camcc CAMCC_CPAS_AHB_CLK>,
> + <&camcc CAMCC_CPHY_RX_CLK_SRC>,
> + <&camcc CAMCC_CSIPHY0_CLK>,
> + <&camcc CAMCC_CSI0PHYTIMER_CLK_SRC>,
> + <&camcc CAMCC_CSI0PHYTIMER_CLK>,
> + <&camcc CAMCC_CSIPHY1_CLK>,
> + <&camcc CAMCC_CSI1PHYTIMER_CLK_SRC>,
> + <&camcc CAMCC_CSI1PHYTIMER_CLK>,
> + <&camcc CAMCC_CSIPHY2_CLK>,
> + <&camcc CAMCC_CSI2PHYTIMER_CLK_SRC>,
> + <&camcc CAMCC_CSI2PHYTIMER_CLK>,
> + <&camcc CAMCC_CSIPHY3_CLK>,
> + <&camcc CAMCC_CSI3PHYTIMER_CLK_SRC>,
> + <&camcc CAMCC_CSI3PHYTIMER_CLK>,
> + <&camcc CAMCC_IFE_0_AXI_CLK>,
> + <&camcc CAMCC_IFE_0_CLK_SRC>,
> + <&camcc CAMCC_IFE_0_CLK>,
> + <&camcc CAMCC_IFE_0_CPHY_RX_CLK>,
> + <&camcc CAMCC_IFE_0_CSID_CLK_SRC>,
> + <&camcc CAMCC_IFE_0_CSID_CLK>,
> + <&camcc CAMCC_IFE_1_AXI_CLK>,
> + <&camcc CAMCC_IFE_1_CLK_SRC>,
> + <&camcc CAMCC_IFE_1_CLK>,
> + <&camcc CAMCC_IFE_1_CPHY_RX_CLK>,
> + <&camcc CAMCC_IFE_1_CSID_CLK_SRC>,
> + <&camcc CAMCC_IFE_1_CSID_CLK>,
> + <&camcc CAMCC_IFE_2_AXI_CLK>,
> + <&camcc CAMCC_IFE_2_CLK_SRC>,
> + <&camcc CAMCC_IFE_2_CLK>,
> + <&camcc CAMCC_IFE_2_CPHY_RX_CLK>,
> + <&camcc CAMCC_IFE_2_CSID_CLK_SRC>,
> + <&camcc CAMCC_IFE_2_CSID_CLK>,
> + <&camcc CAMCC_IFE_3_AXI_CLK>,
> + <&camcc CAMCC_IFE_3_CLK_SRC>,
> + <&camcc CAMCC_IFE_3_CLK>,
> + <&camcc CAMCC_IFE_3_CPHY_RX_CLK>,
> + <&camcc CAMCC_IFE_3_CSID_CLK_SRC>,
> + <&camcc CAMCC_IFE_3_CSID_CLK>,
> + <&camcc CAMCC_IFE_LITE_0_CLK_SRC>,
> + <&camcc CAMCC_IFE_LITE_0_CLK>,
> + <&camcc CAMCC_IFE_LITE_0_CPHY_RX_CLK>,
> + <&camcc CAMCC_IFE_LITE_0_CSID_CLK_SRC>,
> + <&camcc CAMCC_IFE_LITE_0_CSID_CLK>,
> + <&camcc CAMCC_IFE_LITE_1_CLK_SRC>,
> + <&camcc CAMCC_IFE_LITE_1_CLK>,
> + <&camcc CAMCC_IFE_LITE_1_CPHY_RX_CLK>,
> + <&camcc CAMCC_IFE_LITE_1_CSID_CLK_SRC>,
> + <&camcc CAMCC_IFE_LITE_1_CSID_CLK>,
> + <&camcc CAMCC_IFE_LITE_2_CLK_SRC>,
> + <&camcc CAMCC_IFE_LITE_2_CLK>,
> + <&camcc CAMCC_IFE_LITE_2_CPHY_RX_CLK>,
> + <&camcc CAMCC_IFE_LITE_2_CSID_CLK_SRC>,
> + <&camcc CAMCC_IFE_LITE_2_CSID_CLK>,
> + <&camcc CAMCC_IFE_LITE_3_CLK_SRC>,
> + <&camcc CAMCC_IFE_LITE_3_CLK>,
> + <&camcc CAMCC_IFE_LITE_3_CPHY_RX_CLK>,
> + <&camcc CAMCC_IFE_LITE_3_CSID_CLK_SRC>,
> + <&camcc CAMCC_IFE_LITE_3_CSID_CLK>,
> + <&gcc GCC_CAMERA_HF_AXI_CLK>,
> + <&gcc GCC_CAMERA_SF_AXI_CLK>,
> + <&camcc CAMCC_SLOW_AHB_CLK_SRC>;
> +
> + clock-names = "camnoc_axi",
> + "camnoc_axi_src",
> + "cpas_ahb",
> + "cphy_rx_src",
> + "csiphy0",
> + "csiphy0_timer_src",
> + "csiphy0_timer",
> + "csiphy1",
> + "csiphy1_timer_src",
> + "csiphy1_timer",
> + "csiphy2",
> + "csiphy2_timer_src",
> + "csiphy2_timer",
> + "csiphy3",
> + "csiphy3_timer_src",
> + "csiphy3_timer",
> + "vfe0_axi",
> + "vfe0_src",
> + "vfe0",
> + "vfe0_cphy_rx",
> + "vfe0_csid_src",
> + "vfe0_csid",
> + "vfe1_axi",
> + "vfe1_src",
> + "vfe1",
> + "vfe1_cphy_rx",
> + "vfe1_csid_src",
> + "vfe1_csid",
> + "vfe2_axi",
> + "vfe2_src",
> + "vfe2",
> + "vfe2_cphy_rx",
> + "vfe2_csid_src",
> + "vfe2_csid",
> + "vfe3_axi",
> + "vfe3_src",
> + "vfe3",
> + "vfe3_cphy_rx",
> + "vfe3_csid_src",
> + "vfe3_csid",
> + "vfe_lite0_src",
> + "vfe_lite0",
> + "vfe_lite0_cphy_rx",
> + "vfe_lite0_csid_src",
> + "vfe_lite0_csid",
> + "vfe_lite1_src",
> + "vfe_lite1",
> + "vfe_lite1_cphy_rx",
> + "vfe_lite1_csid_src",
> + "vfe_lite1_csid",
> + "vfe_lite2_src",
> + "vfe_lite2",
> + "vfe_lite2_cphy_rx",
> + "vfe_lite2_csid_src",
> + "vfe_lite2_csid",
> + "vfe_lite3_src",
> + "vfe_lite3",
> + "vfe_lite3_cphy_rx",
> + "vfe_lite3_csid_src",
> + "vfe_lite3_csid",
> + "gcc_axi_hf",
> + "gcc_axi_sf",
> + "slow_ahb_src";
> +
> +
> + iommus = <&apps_smmu 0x2000 0x4e0>,
> + <&apps_smmu 0x2020 0x4e0>,
> + <&apps_smmu 0x2040 0x4e0>,
> + <&apps_smmu 0x2060 0x4e0>,
> + <&apps_smmu 0x2080 0x4e0>,
> + <&apps_smmu 0x20e0 0x4e0>,
> + <&apps_smmu 0x20c0 0x4e0>,
> + <&apps_smmu 0x20a0 0x4e0>,
> + <&apps_smmu 0x2400 0x4e0>,
> + <&apps_smmu 0x2420 0x4e0>,
> + <&apps_smmu 0x2440 0x4e0>,
> + <&apps_smmu 0x2460 0x4e0>,
> + <&apps_smmu 0x2480 0x4e0>,
> + <&apps_smmu 0x24e0 0x4e0>,
> + <&apps_smmu 0x24c0 0x4e0>,
> + <&apps_smmu 0x24a0 0x4e0>;
> +
> + interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>,
> + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>,
> + <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>,
> + <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "cam_ahb",
> + "cam_hf_mnoc",
> + "cam_sf_mnoc",
> + "cam_sf_icp_mnoc";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
This looks incomplete. No endpoint?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 4/5] media: dt-bindings: media: camss: Add qcom,sc8280xp-camss binding
2023-10-06 12:33 ` Krzysztof Kozlowski
@ 2023-10-06 12:52 ` Bryan O'Donoghue
2023-10-06 13:42 ` Krzysztof Kozlowski
2023-10-06 15:12 ` Rob Herring
1 sibling, 1 reply; 20+ messages in thread
From: Bryan O'Donoghue @ 2023-10-06 12:52 UTC (permalink / raw)
To: Krzysztof Kozlowski, Bryan O'Donoghue, agross, andersson,
konrad.dybcio, loic.poulain, rfoss, andi.shyti, robh+dt,
krzysztof.kozlowski+dt, conor+dt, todor.too, mchehab
Cc: linux-arm-msm, linux-i2c, linux-media, devicetree, linux-kernel
On 06/10/2023 13:33, Krzysztof Kozlowski wrote:
>> + port@3:
>> + $ref: /schemas/graph.yaml#/$defs/port-base
>> + unevaluatedProperties: false
>> + description:
>> + Input port for receiving CSI data.
> No output ports to some ISP?
Not for the moment anyway. Its a raw dump of bayer data to userspace.
---
bod
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 4/5] media: dt-bindings: media: camss: Add qcom,sc8280xp-camss binding
2023-10-06 12:52 ` Bryan O'Donoghue
@ 2023-10-06 13:42 ` Krzysztof Kozlowski
0 siblings, 0 replies; 20+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-06 13:42 UTC (permalink / raw)
To: Bryan O'Donoghue, Bryan O'Donoghue, agross, andersson,
konrad.dybcio, loic.poulain, rfoss, andi.shyti, robh+dt,
krzysztof.kozlowski+dt, conor+dt, todor.too, mchehab
Cc: linux-arm-msm, linux-i2c, linux-media, devicetree, linux-kernel
On 06/10/2023 14:52, Bryan O'Donoghue wrote:
> On 06/10/2023 13:33, Krzysztof Kozlowski wrote:
>>> + port@3:
>>> + $ref: /schemas/graph.yaml#/$defs/port-base
>>> + unevaluatedProperties: false
>>> + description:
>>> + Input port for receiving CSI data.
>> No output ports to some ISP?
>
> Not for the moment anyway. Its a raw dump of bayer data to userspace.
The best would be if bindings were complete, but I understand.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 4/5] media: dt-bindings: media: camss: Add qcom,sc8280xp-camss binding
2023-10-06 12:33 ` Krzysztof Kozlowski
2023-10-06 12:52 ` Bryan O'Donoghue
@ 2023-10-06 15:12 ` Rob Herring
1 sibling, 0 replies; 20+ messages in thread
From: Rob Herring @ 2023-10-06 15:12 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Bryan O'Donoghue, agross, andersson, konrad.dybcio,
loic.poulain, rfoss, andi.shyti, krzysztof.kozlowski+dt, conor+dt,
todor.too, mchehab, linux-arm-msm, linux-i2c, linux-media,
devicetree, linux-kernel
On Fri, Oct 06, 2023 at 02:33:42PM +0200, Krzysztof Kozlowski wrote:
> On 06/10/2023 14:01, Bryan O'Donoghue wrote:
> > Add bindings for qcom,sc8280xp-camss in order to support the camera
> > subsystem for sc8280xp as found in the Lenovo x13s Laptop.
> >
> > Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> > ---
> > .../bindings/media/qcom,sc8280xp-camss.yaml | 598 ++++++++++++++++++
> > 1 file changed, 598 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.yaml
> > new file mode 100644
> > index 000000000000..46d2da4ad373
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.yaml
> > @@ -0,0 +1,598 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/media/qcom,sc8280xp-camss.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Qualcomm CAMSS
>
> Instead something like:
> Qualcomm SC8280xp Camera SubSystem (CAMSS)
> ?
>
> > +
> > +maintainers:
> > + - Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> > +
> > +description: |
> > + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
> > +
> > +properties:
> > + compatible:
> > + const: qcom,sc8280xp-camss
> > +
> > + clocks:
> > + minItems: 63
>
> You can drop minItems if they equal maxItems.
>
> > + maxItems: 63
> > +
> > + clock-names:
> > + items:
> > + - const: camnoc_axi
> > + - const: camnoc_axi_src
> > + - const: cpas_ahb
> > + - const: cphy_rx_src
> > + - const: csiphy0
> > + - const: csiphy0_timer_src
> > + - const: csiphy0_timer
> > + - const: csiphy1
> > + - const: csiphy1_timer_src
> > + - const: csiphy1_timer
> > + - const: csiphy2
> > + - const: csiphy2_timer_src
> > + - const: csiphy2_timer
> > + - const: csiphy3
> > + - const: csiphy3_timer_src
> > + - const: csiphy3_timer
> > + - const: vfe0_axi
> > + - const: vfe0_src
> > + - const: vfe0
> > + - const: vfe0_cphy_rx
> > + - const: vfe0_csid_src
> > + - const: vfe0_csid
> > + - const: vfe1_axi
> > + - const: vfe1_src
> > + - const: vfe1
> > + - const: vfe1_cphy_rx
> > + - const: vfe1_csid_src
> > + - const: vfe1_csid
> > + - const: vfe2_axi
> > + - const: vfe2_src
> > + - const: vfe2
> > + - const: vfe2_cphy_rx
> > + - const: vfe2_csid_src
> > + - const: vfe2_csid
> > + - const: vfe3_axi
> > + - const: vfe3_src
> > + - const: vfe3
> > + - const: vfe3_cphy_rx
> > + - const: vfe3_csid_src
> > + - const: vfe3_csid
> > + - const: vfe_lite0_src
> > + - const: vfe_lite0
> > + - const: vfe_lite0_cphy_rx
> > + - const: vfe_lite0_csid_src
> > + - const: vfe_lite0_csid
> > + - const: vfe_lite1_src
> > + - const: vfe_lite1
> > + - const: vfe_lite1_cphy_rx
> > + - const: vfe_lite1_csid_src
> > + - const: vfe_lite1_csid
> > + - const: vfe_lite2_src
> > + - const: vfe_lite2
> > + - const: vfe_lite2_cphy_rx
> > + - const: vfe_lite2_csid_src
> > + - const: vfe_lite2_csid
> > + - const: vfe_lite3_src
> > + - const: vfe_lite3
> > + - const: vfe_lite3_cphy_rx
> > + - const: vfe_lite3_csid_src
> > + - const: vfe_lite3_csid
> > + - const: gcc_axi_hf
> > + - const: gcc_axi_sf
> > + - const: slow_ahb_src
> > +
> > + interrupts:
> > + minItems: 20
>
> You can drop minItems if they equal maxItems.
>
>
> > + maxItems: 20
> > +
> > + interrupt-names:
> > + items:
> > + - const: csid1_lite
> > + - const: vfe_lite1
> > + - const: csiphy3
> > + - const: csid0
> > + - const: vfe0
> > + - const: csid1
> > + - const: vfe1
> > + - const: csid0_lite
> > + - const: vfe_lite0
> > + - const: csiphy0
> > + - const: csiphy1
> > + - const: csiphy2
> > + - const: csid2
> > + - const: vfe2
> > + - const: csid3_lite
> > + - const: csid2_lite
> > + - const: vfe_lite3
> > + - const: vfe_lite2
> > + - const: csid3
> > + - const: vfe3
> > +
> > + iommus:
> > + minItems: 16
>
> You can drop minItems if they equal maxItems.
>
> > + maxItems: 16
> > +
> > + interconnects:
> > + minItems: 4
>
> You can drop minItems if they equal maxItems.
>
>
> > + maxItems: 4
> > +
> > + interconnect-names:
> > + items:
> > + - const: cam_ahb
> > + - const: cam_hf_mnoc
> > + - const: cam_sf_mnoc
> > + - const: cam_sf_icp_mnoc
> > +
> > + power-domains:
> > + items:
> > + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
> > + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
> > + - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller.
> > + - description: IFE3 GDSC - Image Front End, Global Distributed Switch Controller.
> > + - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller.
> > +
> > + power-domain-names:
> > + items:
> > + - description: ife0
> > + - description: ife1
> > + - description: ife2
> > + - description: ife3
> > + - description: top
> > +
> > + ports:
> > + $ref: /schemas/graph.yaml#/properties/ports
> > +
>
> On this level of indentation:
> additionalProperties: false
No, because then #size-cells/#address-cells won't be allowed.
Rob
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 4/5] media: dt-bindings: media: camss: Add qcom,sc8280xp-camss binding
2023-10-06 12:01 ` [PATCH 4/5] media: dt-bindings: media: camss: Add qcom,sc8280xp-camss binding Bryan O'Donoghue
2023-10-06 12:33 ` Krzysztof Kozlowski
@ 2023-10-06 13:58 ` Rob Herring
1 sibling, 0 replies; 20+ messages in thread
From: Rob Herring @ 2023-10-06 13:58 UTC (permalink / raw)
To: Bryan O'Donoghue
Cc: konrad.dybcio, andi.shyti, mchehab, conor+dt, linux-i2c,
andersson, linux-media, rfoss, robh+dt, krzysztof.kozlowski+dt,
loic.poulain, linux-kernel, linux-arm-msm, todor.too, agross,
devicetree
On Fri, 06 Oct 2023 13:01:58 +0100, Bryan O'Donoghue wrote:
> Add bindings for qcom,sc8280xp-camss in order to support the camera
> subsystem for sc8280xp as found in the Lenovo x13s Laptop.
>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> ---
> .../bindings/media/qcom,sc8280xp-camss.yaml | 598 ++++++++++++++++++
> 1 file changed, 598 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.yaml: properties:power-domain-names:items: 'oneOf' conditional failed, one must be fixed:
[{'description': 'ife0'}, {'description': 'ife1'}, {'description': 'ife2'}, {'description': 'ife3'}, {'description': 'top'}] is not of type 'object'
Additional properties are not allowed ('description' was unexpected)
from schema $id: http://devicetree.org/meta-schemas/string-array.yaml#
Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.example.dts:26:18: fatal error: dt-bindings/clock/qcom,sc8280xp-camcc.h: No such file or directory
26 | #include <dt-bindings/clock/qcom,sc8280xp-camcc.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[2]: *** [scripts/Makefile.lib:419: Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.example.dtb] Error 1
make[2]: *** Waiting for unfinished jobs....
make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1427: dt_binding_check] Error 2
make: *** [Makefile:234: __sub-make] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20231006120159.3413789-5-bryan.odonoghue@linaro.org
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 5/5] arm64: dts: qcom: sc8280xp: camss: Add CAMSS block definition
2023-10-06 12:01 [PATCH 0/5] Add sc8280xp CCI and CAMSS core dtsi Bryan O'Donoghue
` (3 preceding siblings ...)
2023-10-06 12:01 ` [PATCH 4/5] media: dt-bindings: media: camss: Add qcom,sc8280xp-camss binding Bryan O'Donoghue
@ 2023-10-06 12:01 ` Bryan O'Donoghue
4 siblings, 0 replies; 20+ messages in thread
From: Bryan O'Donoghue @ 2023-10-06 12:01 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, loic.poulain, rfoss, andi.shyti,
robh+dt, krzysztof.kozlowski+dt, conor+dt, todor.too, mchehab,
bryan.odonoghue
Cc: linux-arm-msm, linux-i2c, linux-media, devicetree, linux-kernel
Add CAMSS block definition for sc8280xp.
This drop contains definitions for the following components on sc8280xp:
VFE * 4
VFE Lite * 4
CSID * 4
CSIPHY * 4
This dtsi definition has been developed and validated on a Lenovo X13s
laptop.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 285 +++++++++++++++++++++++++
1 file changed, 285 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 199b112da295..58bea7617666 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -3615,6 +3615,291 @@ cci3_i2c1: i2c-bus@1 {
};
};
+ camss: camss@ac5a000 {
+ compatible = "qcom,sc8280xp-camss";
+
+ reg = <0 0x0ac5a000 0 0x2000>,
+ <0 0x0ac5c000 0 0x2000>,
+ <0 0x0ac65000 0 0x2000>,
+ <0 0x0ac67000 0 0x2000>,
+ <0 0x0acaf000 0 0x4000>,
+ <0 0x0acb3000 0 0x1000>,
+ <0 0x0acb6000 0 0x4000>,
+ <0 0x0acba000 0 0x1000>,
+ <0 0x0acbd000 0 0x4000>,
+ <0 0x0acc1000 0 0x1000>,
+ <0 0x0acc4000 0 0x4000>,
+ <0 0x0acc8000 0 0x1000>,
+ <0 0x0accb000 0 0x4000>,
+ <0 0x0accf000 0 0x1000>,
+ <0 0x0acd2000 0 0x4000>,
+ <0 0x0acd6000 0 0x1000>,
+ <0 0x0acd9000 0 0x4000>,
+ <0 0x0acdd000 0 0x1000>,
+ <0 0x0ace0000 0 0x4000>,
+ <0 0x0ace4000 0 0x1000>;
+
+ reg-names = "csiphy2",
+ "csiphy3",
+ "csiphy0",
+ "csiphy1",
+ "vfe0",
+ "csid0",
+ "vfe1",
+ "csid1",
+ "vfe2",
+ "csid2",
+ "vfe_lite0",
+ "csid0_lite",
+ "vfe_lite1",
+ "csid1_lite",
+ "vfe_lite2",
+ "csid2_lite",
+ "vfe_lite3",
+ "csid3_lite",
+ "vfe3",
+ "csid3";
+
+ interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-names = "csid1_lite",
+ "vfe_lite1",
+ "csiphy3",
+ "csid0",
+ "vfe0",
+ "csid1",
+ "vfe1",
+ "csid0_lite",
+ "vfe_lite0",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csid2",
+ "vfe2",
+ "csid3_lite",
+ "csid2_lite",
+ "vfe_lite3",
+ "vfe_lite2",
+ "csid3",
+ "vfe3";
+
+ power-domains = <&camcc IFE_0_GDSC>,
+ <&camcc IFE_1_GDSC>,
+ <&camcc IFE_2_GDSC>,
+ <&camcc IFE_3_GDSC>,
+ <&camcc TITAN_TOP_GDSC>;
+
+ power-domain-names = "ife0",
+ "ife1",
+ "ife2",
+ "ife3",
+ "top";
+
+ clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
+ <&camcc CAMCC_CAMNOC_AXI_CLK_SRC>,
+ <&camcc CAMCC_CPAS_AHB_CLK>,
+ <&camcc CAMCC_CPHY_RX_CLK_SRC>,
+ <&camcc CAMCC_CSIPHY0_CLK>,
+ <&camcc CAMCC_CSI0PHYTIMER_CLK_SRC>,
+ <&camcc CAMCC_CSI0PHYTIMER_CLK>,
+ <&camcc CAMCC_CSIPHY1_CLK>,
+ <&camcc CAMCC_CSI1PHYTIMER_CLK_SRC>,
+ <&camcc CAMCC_CSI1PHYTIMER_CLK>,
+ <&camcc CAMCC_CSIPHY2_CLK>,
+ <&camcc CAMCC_CSI2PHYTIMER_CLK_SRC>,
+ <&camcc CAMCC_CSI2PHYTIMER_CLK>,
+ <&camcc CAMCC_CSIPHY3_CLK>,
+ <&camcc CAMCC_CSI3PHYTIMER_CLK_SRC>,
+ <&camcc CAMCC_CSI3PHYTIMER_CLK>,
+ <&camcc CAMCC_IFE_0_AXI_CLK>,
+ <&camcc CAMCC_IFE_0_CLK_SRC>,
+ <&camcc CAMCC_IFE_0_CLK>,
+ <&camcc CAMCC_IFE_0_CPHY_RX_CLK>,
+ <&camcc CAMCC_IFE_0_CSID_CLK_SRC>,
+ <&camcc CAMCC_IFE_0_CSID_CLK>,
+ <&camcc CAMCC_IFE_1_AXI_CLK>,
+ <&camcc CAMCC_IFE_1_CLK_SRC>,
+ <&camcc CAMCC_IFE_1_CLK>,
+ <&camcc CAMCC_IFE_1_CPHY_RX_CLK>,
+ <&camcc CAMCC_IFE_1_CSID_CLK_SRC>,
+ <&camcc CAMCC_IFE_1_CSID_CLK>,
+ <&camcc CAMCC_IFE_2_AXI_CLK>,
+ <&camcc CAMCC_IFE_2_CLK_SRC>,
+ <&camcc CAMCC_IFE_2_CLK>,
+ <&camcc CAMCC_IFE_2_CPHY_RX_CLK>,
+ <&camcc CAMCC_IFE_2_CSID_CLK_SRC>,
+ <&camcc CAMCC_IFE_2_CSID_CLK>,
+ <&camcc CAMCC_IFE_3_AXI_CLK>,
+ <&camcc CAMCC_IFE_3_CLK_SRC>,
+ <&camcc CAMCC_IFE_3_CLK>,
+ <&camcc CAMCC_IFE_3_CPHY_RX_CLK>,
+ <&camcc CAMCC_IFE_3_CSID_CLK_SRC>,
+ <&camcc CAMCC_IFE_3_CSID_CLK>,
+ <&camcc CAMCC_IFE_LITE_0_CLK_SRC>,
+ <&camcc CAMCC_IFE_LITE_0_CLK>,
+ <&camcc CAMCC_IFE_LITE_0_CPHY_RX_CLK>,
+ <&camcc CAMCC_IFE_LITE_0_CSID_CLK_SRC>,
+ <&camcc CAMCC_IFE_LITE_0_CSID_CLK>,
+ <&camcc CAMCC_IFE_LITE_1_CLK_SRC>,
+ <&camcc CAMCC_IFE_LITE_1_CLK>,
+ <&camcc CAMCC_IFE_LITE_1_CPHY_RX_CLK>,
+ <&camcc CAMCC_IFE_LITE_1_CSID_CLK_SRC>,
+ <&camcc CAMCC_IFE_LITE_1_CSID_CLK>,
+ <&camcc CAMCC_IFE_LITE_2_CLK_SRC>,
+ <&camcc CAMCC_IFE_LITE_2_CLK>,
+ <&camcc CAMCC_IFE_LITE_2_CPHY_RX_CLK>,
+ <&camcc CAMCC_IFE_LITE_2_CSID_CLK_SRC>,
+ <&camcc CAMCC_IFE_LITE_2_CSID_CLK>,
+ <&camcc CAMCC_IFE_LITE_3_CLK_SRC>,
+ <&camcc CAMCC_IFE_LITE_3_CLK>,
+ <&camcc CAMCC_IFE_LITE_3_CPHY_RX_CLK>,
+ <&camcc CAMCC_IFE_LITE_3_CSID_CLK_SRC>,
+ <&camcc CAMCC_IFE_LITE_3_CSID_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&gcc GCC_CAMERA_SF_AXI_CLK>,
+ <&camcc CAMCC_SLOW_AHB_CLK_SRC>;
+
+ clock-names = "camnoc_axi",
+ "camnoc_axi_src",
+ "cpas_ahb",
+ "cphy_rx_src",
+ "csiphy0",
+ "csiphy0_timer_src",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer_src",
+ "csiphy1_timer",
+ "csiphy2",
+ "csiphy2_timer_src",
+ "csiphy2_timer",
+ "csiphy3",
+ "csiphy3_timer_src",
+ "csiphy3_timer",
+ "vfe0_axi",
+ "vfe0_src",
+ "vfe0",
+ "vfe0_cphy_rx",
+ "vfe0_csid_src",
+ "vfe0_csid",
+ "vfe1_axi",
+ "vfe1_src",
+ "vfe1",
+ "vfe1_cphy_rx",
+ "vfe1_csid_src",
+ "vfe1_csid",
+ "vfe2_axi",
+ "vfe2_src",
+ "vfe2",
+ "vfe2_cphy_rx",
+ "vfe2_csid_src",
+ "vfe2_csid",
+ "vfe3_axi",
+ "vfe3_src",
+ "vfe3",
+ "vfe3_cphy_rx",
+ "vfe3_csid_src",
+ "vfe3_csid",
+ "vfe_lite0_src",
+ "vfe_lite0",
+ "vfe_lite0_cphy_rx",
+ "vfe_lite0_csid_src",
+ "vfe_lite0_csid",
+ "vfe_lite1_src",
+ "vfe_lite1",
+ "vfe_lite1_cphy_rx",
+ "vfe_lite1_csid_src",
+ "vfe_lite1_csid",
+ "vfe_lite2_src",
+ "vfe_lite2",
+ "vfe_lite2_cphy_rx",
+ "vfe_lite2_csid_src",
+ "vfe_lite2_csid",
+ "vfe_lite3_src",
+ "vfe_lite3",
+ "vfe_lite3_cphy_rx",
+ "vfe_lite3_csid_src",
+ "vfe_lite3_csid",
+ "gcc_axi_hf",
+ "gcc_axi_sf",
+ "slow_ahb_src";
+
+ iommus = <&apps_smmu 0x2000 0x4e0>,
+ <&apps_smmu 0x2020 0x4e0>,
+ <&apps_smmu 0x2040 0x4e0>,
+ <&apps_smmu 0x2060 0x4e0>,
+ <&apps_smmu 0x2080 0x4e0>,
+ <&apps_smmu 0x20e0 0x4e0>,
+ <&apps_smmu 0x20c0 0x4e0>,
+ <&apps_smmu 0x20a0 0x4e0>,
+ <&apps_smmu 0x2400 0x4e0>,
+ <&apps_smmu 0x2420 0x4e0>,
+ <&apps_smmu 0x2440 0x4e0>,
+ <&apps_smmu 0x2460 0x4e0>,
+ <&apps_smmu 0x2480 0x4e0>,
+ <&apps_smmu 0x24e0 0x4e0>,
+ <&apps_smmu 0x24c0 0x4e0>,
+ <&apps_smmu 0x24a0 0x4e0>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>,
+ <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>,
+ <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>,
+ <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "cam_ahb",
+ "cam_hf_mnoc",
+ "cam_sf_mnoc",
+ "cam_sf_icp_mnoc";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ port@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ port@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
+
camcc: clock-controller@ad00000 {
compatible = "qcom,sc8280xp-camcc";
reg = <0 0x0ad00000 0 0x20000>;
--
2.40.1
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