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[88.156.142.67]) by smtp.gmail.com with ESMTPSA id bf19-20020a2eaa13000000b0026bf43a4d72sm175158ljb.115.2022.11.29.06.46.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 29 Nov 2022 06:46:49 -0800 (PST) Message-ID: Date: Tue, 29 Nov 2022 15:46:48 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.5.0 Subject: Re: [PATCH 3/8] dt-bindings: soc: socionext: Add UniPhier peripheral block Content-Language: en-US To: Kunihiko Hayashi , Rob Herring , Krzysztof Kozlowski Cc: Masami Hiramatsu , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20221129103509.9958-1-hayashi.kunihiko@socionext.com> <20221129103509.9958-4-hayashi.kunihiko@socionext.com> From: Krzysztof Kozlowski In-Reply-To: <20221129103509.9958-4-hayashi.kunihiko@socionext.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 29/11/2022 11:35, Kunihiko Hayashi wrote: > Add devicetree binding schema for the peripheral block implemented on > Socionext Uniphier SoCs. > > Peripheral block implemented on Socionext UniPhier SoCs is an integrated > component of the peripherals including UART, I2C/FI2C, and SCSSI. > > Peripheral block has some function logics to control the component. > > Signed-off-by: Kunihiko Hayashi > --- > .../socionext,uniphier-perictrl.yaml | 67 +++++++++++++++++++ > 1 file changed, 67 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml > > diff --git a/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml > new file mode 100644 > index 000000000000..080b6ab3ea1a > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml > @@ -0,0 +1,67 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-perictrl.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Socionext UniPhier peripheral block controller > + > +maintainers: > + - Kunihiko Hayashi > + > +description: |+ > + Peripheral block implemented on Socionext UniPhier SoCs is an integrated > + component of the peripherals including UART, I2C/FI2C, and SCSSI. > + Peripheral block controller is a logic to control the component. > + > +properties: > + compatible: > + items: > + - enum: > + - socionext,uniphier-ld4-perictrl > + - socionext,uniphier-pro4-perictrl > + - socionext,uniphier-pro5-perictrl > + - socionext,uniphier-pxs2-perictrl > + - socionext,uniphier-ld6b-perictrl > + - socionext,uniphier-sld8-perictrl > + - socionext,uniphier-ld11-perictrl > + - socionext,uniphier-ld20-perictrl > + - socionext,uniphier-pxs3-perictrl > + - socionext,uniphier-nx1-perictrl > + - socionext,uniphier-perictrl > + - const: simple-mfd > + - const: syscon > + > + reg: > + maxItems: 1 > + > +patternProperties: > + "^clock-controller(@[0-9a-f]+)?$": > + $ref: /schemas/clock/socionext,uniphier-clock.yaml# > + > + "^reset-controller(@[0-9a-f]+)?$": > + $ref: /schemas/reset/socionext,uniphier-reset.yaml# > + > +required: > + - compatible > + - reg > + > +additionalProperties: false > + > +examples: > + - | > + syscon@59820000 { > + compatible = "socionext,uniphier-ld20-perictrl", > + "simple-mfd", "syscon"; > + reg = <0x59820000 0x200>; > + > + clock-controller { None of your children in examples and in DTS have unit addresses. However you explicitly mentioned them in the patternProperties. Do you expect adding unit addresses? Best regards, Krzysztof