From: Christian Bruel <christian.bruel@foss.st.com>
To: Manivannan Sadhasivam <mani@kernel.org>,
Bjorn Helgaas <helgaas@kernel.org>
Cc: Vincent Guittot <vincent.guittot@linaro.org>,
<chester62515@gmail.com>, <mbrugger@suse.com>,
<ghennadi.procopciuc@oss.nxp.com>, <s32@nxp.com>,
<bhelgaas@google.com>, <jingoohan1@gmail.com>,
<lpieralisi@kernel.org>, <kwilczynski@kernel.org>,
<robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>,
<Ionut.Vicovan@nxp.com>, <larisa.grigore@nxp.com>,
<Ghennadi.Procopciuc@nxp.com>, <ciprianmarian.costea@nxp.com>,
<bogdan.hamciuc@nxp.com>, <Frank.li@nxp.com>,
<linux-arm-kernel@lists.infradead.org>,
<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <imx@lists.linux.dev>,
<cassel@kernel.org>, Richard Zhu <hongxing.zhu@nxp.com>,
Lucas Stach <l.stach@pengutronix.de>,
Minghuan Lian <minghuan.Lian@nxp.com>,
Mingkai Hu <mingkai.hu@nxp.com>, Roy Zang <roy.zang@nxp.com>,
<linux-stm32@st-md-mailman.stormreply.com>
Subject: Re: [PATCH 3/4 v3] PCI: s32g: Add initial PCIe support (RC)
Date: Fri, 14 Nov 2025 11:05:45 +0100 [thread overview]
Message-ID: <b945e463-52ec-417c-8e6a-599c35a6727d@foss.st.com> (raw)
In-Reply-To: <vrgjkulv22hzbx65olh3zpyqxq6dr7d5mepngjwgc3gudjoxwo@ll7xc2teya2s>
>>
>> The implication is that *every* user of dw_pcie_suspend_noirq() would
>> have to check for the link being up. There are only three existing
>> callers:
>>
>> imx_pcie_suspend_noirq()
>> ls_pcie_suspend_noirq()
>> stm32_pcie_suspend_noirq()
>>
>> but none of them checks for the link being up.
>>
stm32 supports L1.1, so we bail out before pme_turn_off() in
dw_pcie_suspend_noirq()
>
> If no devices are attached to the bus, then there is no need to broadcast
> PME_Turn_Off and wait for L2/L3. I've just sent out a series that fixes it [1].
> Hopefully, this will allow Vincent to use dw_pcie_{suspend/resume}_noirq() APIs.
>
> - Mani
>
> [1] https://lore.kernel.org/linux-pci/20251106061326.8241-1-manivannan.sadhasivam@oss.qualcomm.com/
dw_pcie_suspend_noirq() path tested OK on stm32mp2.
Regards
Christian
next prev parent reply other threads:[~2025-11-14 10:06 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-22 17:43 [PATCH 0/4 v3] PCI: s32g: Add support for PCIe controller Vincent Guittot
2025-10-22 17:43 ` [PATCH 1/4 v3] dt-bindings: PCI: s32g: Add NXP " Vincent Guittot
2025-10-22 19:17 ` Frank Li
2025-10-24 6:58 ` Vincent Guittot
2025-11-06 0:00 ` Bjorn Helgaas
2025-11-06 7:51 ` Vincent Guittot
2025-11-06 7:12 ` Manivannan Sadhasivam
2025-11-06 8:09 ` Vincent Guittot
2025-11-06 17:38 ` Bjorn Helgaas
2025-11-10 9:14 ` Vincent Guittot
2025-10-22 17:43 ` [PATCH 2/4 v3] PCI: dw: Add more registers and bitfield definition Vincent Guittot
2025-10-22 17:43 ` [PATCH 3/4 v3] PCI: s32g: Add initial PCIe support (RC) Vincent Guittot
2025-10-22 19:04 ` Bjorn Helgaas
2025-10-24 6:50 ` Vincent Guittot
2025-11-05 10:28 ` Niklas Cassel
2025-11-05 10:43 ` Ilpo Järvinen
2025-11-05 11:00 ` Niklas Cassel
2025-11-06 0:05 ` Bjorn Helgaas
2025-11-06 6:24 ` Manivannan Sadhasivam
2025-11-06 7:50 ` Vincent Guittot
2025-11-14 10:05 ` Christian Bruel [this message]
2025-11-14 21:35 ` Bjorn Helgaas
2025-11-06 7:46 ` Vincent Guittot
2025-10-22 19:44 ` Frank Li
2025-10-24 6:53 ` Vincent Guittot
2025-11-05 7:58 ` Vincent Guittot
2025-11-06 17:23 ` Bjorn Helgaas
2025-11-06 17:33 ` Vincent Guittot
2025-10-22 17:43 ` [PATCH 4/4 v3] MAINTAINERS: Add MAINTAINER for NXP S32G PCIe driver Vincent Guittot
2025-10-22 19:20 ` Frank Li
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