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Mon, 13 Jul 2026 05:31:47 -0700 (PDT) X-Received: by 2002:a05:622a:1195:b0:51c:93b:4f1c with SMTP id d75a77b69052e-51cbf1fd6b7mr81466271cf.43.1783945906795; Mon, 13 Jul 2026 05:31:46 -0700 (PDT) Received: from [10.218.5.114] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5b01caa635dsm2861932e87.62.2026.07.13.05.31.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 13 Jul 2026 05:31:45 -0700 (PDT) Message-ID: Date: Mon, 13 Jul 2026 18:01:34 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 4/4] arm64: dts: qcom: shikra: Add support for AudioCoreCC and AudioCoreCSR nodes To: Konrad Dybcio , Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20260708-shikra-audiocorecc-v2-0-b320d822cdd0@oss.qualcomm.com> <20260708-shikra-audiocorecc-v2-4-b320d822cdd0@oss.qualcomm.com> <71576059-b5cd-401e-b4b0-c1784f24ba46@oss.qualcomm.com> <81ac9bcb-65c8-4cd5-bc54-c350f24d06a8@oss.qualcomm.com> Content-Language: en-US From: Imran Shaik In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYwNzEzMDEzMCBTYWx0ZWRfXxSSTwIMPDCE2 9TkOwU8qSyUZvGpztsM6RQk0nVC+y2Zyrt6MirIg1nzOM3rFxHXwtAVlbKIvY/dMp88FV6aPNHu a9IKheCp5dSF853i2ZvtPyPOMa07uU8= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzEzMDEzMCBTYWx0ZWRfX/CVjlJ2aGK9O D4YJZoGKL7hdaNU2qN6hU4wZ0rq7deJqAe6lHKPmfTjRwUG5/vLHQYp+K7/IE8HK/l4iJpM39Rn aE6tol3spf8VlD6ZZMedaQCJW1SZ5tm9w1bqxTTZIEzfwgQ7lwPN/a9HI6gOEWCboeWnKGCFCCe xN4CDhBLO8BNv4wHH4j9tjBetXJI5f02o661JQeFBdf1WmupUvACLwxjmm+ExyXOi3YsIr1c/se NawYN5fnutx2Jwm3JO5BCkj7G+uBK8v812g5mzhXjjYMszdLBwA/A4MJ0kW/xEBm37RAvaqROtw P0p7inOS4Tp96bKjYan4oWI9tdWwTeCOGSxBar643VcGWajs0HLGe2bPUPsv9PA3Y0jc3h7ZmK8 LY8RCaxTGWtOFIj12eaur/evoUZXmjXl3//ctLYLjZl8vdM/G8I+X+0R0TGQAn0UKvCp2cUll8s LeKEEmuQtPv5DndLpWQ== X-Proofpoint-ORIG-GUID: F8LIBp-awFaIj3wSP3Jrm-7o0ForN8-Q X-Authority-Analysis: v=2.4 cv=DbcnbPtW c=1 sm=1 tr=0 ts=6a54dab3 cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=-Cfwf-izUa4NwULDX60A:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-GUID: F8LIBp-awFaIj3wSP3Jrm-7o0ForN8-Q X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-13_03,2026-07-10_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 priorityscore=1501 phishscore=0 suspectscore=0 bulkscore=0 adultscore=0 spamscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607130130 On 13-07-2026 05:44 pm, Konrad Dybcio wrote: > On 7/13/26 2:07 PM, Imran Shaik wrote: >> >> >> On 09-07-2026 05:30 pm, Konrad Dybcio wrote: >>> On 7/8/26 8:25 PM, Imran Shaik wrote: >>>> Add support for Audio Core Clock Controller (AudioCoreCC) and Audio Core >>>> CSR nodes on Qualcomm Shikra SoC. The Audio Core Clocks and Resets support >>>> differs across Shikra variants based on Audio subsystem enablement as >>>> follows: >>>> - CQM variant: The QAIF driver runs on HLOS, hence both clocks and resets >>>> are required to be supported on HLOS. >>>> - CQS variant: The QAIF driver runs on the Modem, and required clocks are >>>> handled on Modem, so from HLOS only resets are needed. >>>> - IQS variant: no soundwire codes, hence no clocks/resets are needed. >>>> >>>> Signed-off-by: Imran Shaik >>>> --- >>> >>> For the sake of simplification, can the resets be enabled >>> globally by default? >>> >> >> By default (PoR), those resets are under HW control. For audio use cases, software desserts/asserts for switching to SW control. Hence, these cannot be enabled globally by default. > > What does enabling the provider node have to do with changing the > state of the resources? > My bad, I interpreted it in wrong way. We have IQS variant, where we don't have the soundwire codes, and hence the respective clocks/resets are not required to be supported. Due to this, I have kept the status disabled, and enabling only where it is required. > FWIW there's nothing like reset_sync_state > Sure, I can keep the audiocore_csr node enabled by default. > Konrad