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[75.72.117.212]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-5b7bd24d5e9sm4708226173.3.2025.11.17.09.12.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 17 Nov 2025 09:12:44 -0800 (PST) Message-ID: Date: Mon, 17 Nov 2025 11:12:41 -0600 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 0/7] Introduce SpacemiT K1 PCIe phy and host controller To: Jason Montleon Cc: dlan@gentoo.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, kishon@kernel.org, bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, ziyao@disroot.org, aurelien@aurel32.net, johannes@erdfelt.com, mayank.rana@oss.qualcomm.com, qiang.yu@oss.qualcomm.com, shradha.t@samsung.com, inochiama@gmail.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, p.zabel@pengutronix.de, christian.bruel@foss.st.com, thippeswamy.havalige@amd.com, krishna.chundru@oss.qualcomm.com, guodong@riscstar.com, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, spacemit@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org References: <20251113214540.2623070-1-elder@riscstar.com> Content-Language: en-US From: Alex Elder In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 11/14/25 10:21 PM, Jason Montleon wrote: > On Thu, Nov 13, 2025 at 4:45 PM Alex Elder wrote: >> >> This series introduces a PHY driver and a PCIe driver to support PCIe >> on the SpacemiT K1 SoC. The PCIe implementation is derived from a >> Synopsys DesignWare PCIe IP. The PHY driver supports one combination >> PCIe/USB PHY as well as two PCIe-only PHYs. The combo PHY port uses >> one PCIe lane, and the other two ports each have two lanes. All PCIe >> ports operate at 5 GT/second. >> >> The PCIe PHYs must be configured using a value that can only be >> determined using the combo PHY, operating in PCIe mode. To allow >> that PHY to be used for USB, the needed calibration step is performed >> by the PHY driver automatically at probe time. Once this step is done, >> the PHY can be used for either PCIe or USB. >> >> The driver supports 256 MSIs, and initially does not support PCI INTx >> interrupts. The hardware does not support MSI-X. >> >> Version 6 of this series addresses a few comments from Christophe >> Jaillet, and improves a workaround that disables ASPM L1. The two >> people who had reported errors on earlier versions of this code have >> confirmed their NVMe devices now work when configured with the default >> RISC-V kernel configuration. > > I successfully tested this patchset on a Banana Pi F3 and also a > Milk-V M1 Jupiter by making the same additions to k1-milkv-jupiter.dts > as were made to k1-bananapi-f3.dts. > I no longer have problems with NVME devices like I did when I tried v3 and v4. > > Tested-by: Jason Montleon Thank you very much for testing this. Your Tested-by is included in Mani's commit. -Alex