Re: [PATCH v16 4/8] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0

Re: [PATCH v16 4/8] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0

[Fei Shao]

On Mon, Mar 7, 2022 at 11:30 AM jason-jh.lin <jason-jh.lin@mediatek.com> wrote:
>
> Add mt8195 vdosys0 clock driver name and routing table to
> the driver data of mtk-mmsys.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

We've verified this on MT8195 on our end, so
Tested-by: Fei Shao <fshao@chromium.org>


> ---
> Impelmentation patch of vdosys1 can be refered to [1]
>
> [1] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
> - https://patchwork.kernel.org/project/linux-mediatek/patch/20220222100741.30138-6-nancy.lin@mediatek.com/
> ---
>
>  drivers/soc/mediatek/mt8195-mmsys.h    | 130 +++++++++++++++++++++++++
>  drivers/soc/mediatek/mtk-mmsys.c       |  11 +++
>  include/linux/soc/mediatek/mtk-mmsys.h |   9 ++
>  3 files changed, 150 insertions(+)
>  create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> new file mode 100644
> index 000000000000..24a3afe23bc8
> --- /dev/null
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -0,0 +1,130 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
> +#define __SOC_MEDIATEK_MT8195_MMSYS_H
> +
> +#define MT8195_VDO0_OVL_MOUT_EN                                        0xf14
> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0                    BIT(0)
> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0                    BIT(1)
> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1                     BIT(2)
> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1                    BIT(4)
> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1                    BIT(5)
> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0                     BIT(6)
> +
> +#define MT8195_VDO0_SEL_IN                                     0xf34
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK                      GENMASK(1, 0)
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT             (0 << 0)
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1              (1 << 0)
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0             (2 << 0)
> +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK                   GENMASK(4, 4)
> +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0           (0 << 4)
> +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE              (1 << 4)
> +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK                   GENMASK(5, 5)
> +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1           (0 << 5)
> +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE              (1 << 5)
> +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK                  GENMASK(8, 8)
> +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE             (0 << 8)
> +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT         (1 << 8)
> +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK                  GENMASK(9, 9)
> +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT         (0 << 9)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_MASK                       GENMASK(13, 12)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT              (0 << 0)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE                  (1 << 12)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0              (2 << 12)
> +#define MT8195_SEL_IN_DSI0_FROM_MASK                           GENMASK(16, 16)
> +#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT                  (0 << 16)
> +#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0                   (1 << 16)
> +#define MT8195_SEL_IN_DSI1_FROM_MASK                           GENMASK(17, 17)
> +#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT                  (0 << 17)
> +#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE                      (1 << 17)
> +#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK                     GENMASK(20, 20)
> +#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1                        (0 << 20)
> +#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE                        (1 << 20)
> +#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK                      GENMASK(21, 21)
> +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN          (0 << 21)
> +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1          (1 << 21)
> +#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK                     GENMASK(22, 22)
> +#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0                        (0 << 22)
> +
> +#define MT8195_VDO0_SEL_OUT                                    0xf38
> +#define MT8195_SOUT_DISP_DITHER0_TO_MASK                       BIT(0)
> +#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN               (0 << 0)
> +#define MT8195_SOUT_DISP_DITHER0_TO_DSI0                       (1 << 0)
> +#define MT8195_SOUT_DISP_DITHER1_TO_MASK                       GENMASK(2, 1)
> +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN               (0 << 1)
> +#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE                  (1 << 1)
> +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT              (2 << 1)
> +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK                      GENMASK(4, 4)
> +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE                 (0 << 4)
> +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0                  (1 << 4)
> +#define MT8195_SOUT_VPP_MERGE_TO_MASK                          GENMASK(10, 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSI1                          (0 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0                      (1 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0                 (2 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1                    (3 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN                  (4 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK             GENMASK(11, 11)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN                  (0 << 11)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK                      GENMASK(13, 12)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0                      (0 << 12)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0             (1 << 12)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE                 (2 << 12)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK                      GENMASK(17, 16)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1                      (0 << 16)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0                  (1 << 16)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0             (2 << 16)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE                 (3 << 16)
> +
> +static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> +       {
> +               DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> +               MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
> +               MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
> +       }, {
> +               DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
> +               MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
> +               MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
> +       }, {
> +               DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> +               MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> +               MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
> +       }, {
> +               DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
> +               MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
> +               MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
> +       }, {
> +               DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> +               MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
> +               MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
> +       }, {
> +               DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
> +               MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
> +               MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
> +       }, {
> +               DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> +               MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
> +               MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
> +       }, {
> +               DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> +               MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
> +               MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
> +       }, {
> +               DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> +               MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
> +               MT8195_SOUT_DISP_DITHER0_TO_DSI0
> +       }, {
> +               DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
> +               MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> +               MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
> +       }, {
> +               DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> +               MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> +               MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
> +       }, {
> +               DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
> +               MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> +               MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
> +       }
> +};
> +
> +#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 4fc4c2c9ea20..dc5c51f0ccc8 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -17,6 +17,7 @@
>  #include "mt8183-mmsys.h"
>  #include "mt8186-mmsys.h"
>  #include "mt8192-mmsys.h"
> +#include "mt8195-mmsys.h"
>  #include "mt8365-mmsys.h"
>
>  static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> @@ -72,6 +73,12 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
>         .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
>  };
>
> +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
> +       .clk_driver = "clk-mt8195-vdo0",
> +       .routes = mmsys_mt8195_routing_table,
> +       .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> +};
> +
>  static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
>         .clk_driver = "clk-mt8365-mm",
>         .routes = mt8365_mmsys_routing_table,
> @@ -260,6 +267,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
>                 .compatible = "mediatek,mt8192-mmsys",
>                 .data = &mt8192_mmsys_driver_data,
>         },
> +       {
> +               .compatible = "mediatek,mt8195-vdosys0",
> +               .data = &mt8195_vdosys0_driver_data,
> +       },
>         {
>                 .compatible = "mediatek,mt8365-mmsys",
>                 .data = &mt8365_mmsys_driver_data,
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 4bba275e235a..64c77c4a6c56 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -17,13 +17,22 @@ enum mtk_ddp_comp_id {
>         DDP_COMPONENT_COLOR0,
>         DDP_COMPONENT_COLOR1,
>         DDP_COMPONENT_DITHER,
> +       DDP_COMPONENT_DP_INTF0,
>         DDP_COMPONENT_DPI0,
>         DDP_COMPONENT_DPI1,
> +       DDP_COMPONENT_DSC0,
> +       DDP_COMPONENT_DSC1,
>         DDP_COMPONENT_DSI0,
>         DDP_COMPONENT_DSI1,
>         DDP_COMPONENT_DSI2,
>         DDP_COMPONENT_DSI3,
>         DDP_COMPONENT_GAMMA,
> +       DDP_COMPONENT_MERGE0,
> +       DDP_COMPONENT_MERGE1,
> +       DDP_COMPONENT_MERGE2,
> +       DDP_COMPONENT_MERGE3,
> +       DDP_COMPONENT_MERGE4,
> +       DDP_COMPONENT_MERGE5,
>         DDP_COMPONENT_OD0,
>         DDP_COMPONENT_OD1,
>         DDP_COMPONENT_OVL0,
> --
> 2.18.0
>

Re: [PATCH v16 3/8] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding

[AngeloGioacchino Del Regno]

Il 07/03/22 04:28, jason-jh.lin ha scritto:
> There are 2 mmsys, namely vdosys0 and vdosys1 in mt8195.
> Each of them is bound to a display pipeline, so add their
> definition in mtk-mmsys documentation with 2 compatibles.
> 
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml        | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> index 6c2c3edcd443..c5ba515cb0d7 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> @@ -32,6 +32,8 @@ properties:
>                 - mediatek,mt8186-mmsys
>                 - mediatek,mt8192-mmsys
>                 - mediatek,mt8365-mmsys
> +              - mediatek,mt8195-vdosys0
> +              - mediatek,mt8195-vdosys1
>             - const: syscon
>         - items:
>             - const: mediatek,mt7623-mmsys

Re: [PATCH v16 1/8] dt-bindings: soc: mediatek: move out common module from display folder

[AngeloGioacchino Del Regno]

Il 07/03/22 04:28, jason-jh.lin ha scritto:
> From: jason-jh lin <jason-jh.lin@mediatek.corp-partner.google.com>
> 
> AAL, COLOR, CCORR, MUTEX, WDMA could be used by other modules,
> such as MDP, so move their binding document into the common folder.
> 
> Signed-off-by: jason-jh lin <jason-jh.lin@mediatek.corp-partner.google.com>

Hello jason-jh,

I understand that these dt-bindings can eventually be reused by MDP3, and
this change is welcome, as duplication wouldn't be sane, however, this is
not the right series for that to happen.

If you want to move these bindings around, you should do that in the patch
series that actually also adds the compatibles for MDP3 in these modules.

If there's no MDP3-specific compatible for these modules, then you should
not move them from display, as this is documentation for mediatek-drm and
it's (currently) the only provider of these.

Please remove this patch from the vdosys0 series for MT8195 because it is
not adding any compatible that justifies moving these YAML around.

Regards,
Angelo

> ---
>   .../{display => soc}/mediatek/mediatek,aal.yaml     | 13 ++++---------
>   .../{display => soc}/mediatek/mediatek,ccorr.yaml   | 13 ++++---------
>   .../{display => soc}/mediatek/mediatek,color.yaml   | 13 ++++---------
>   .../{display => soc}/mediatek/mediatek,mutex.yaml   | 12 +++---------
>   .../{display => soc}/mediatek/mediatek,wdma.yaml    |  9 ++-------
>   5 files changed, 17 insertions(+), 43 deletions(-)
>   rename Documentation/devicetree/bindings/{display => soc}/mediatek/mediatek,aal.yaml (81%)
>   rename Documentation/devicetree/bindings/{display => soc}/mediatek/mediatek,ccorr.yaml (80%)
>   rename Documentation/devicetree/bindings/{display => soc}/mediatek/mediatek,color.yaml (83%)
>   rename Documentation/devicetree/bindings/{display => soc}/mediatek/mediatek,mutex.yaml (82%)
>   rename Documentation/devicetree/bindings/{display => soc}/mediatek/mediatek,wdma.yaml (85%)
> 
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,aal.yaml
> similarity index 81%
> rename from Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
> rename to Documentation/devicetree/bindings/soc/mediatek/mediatek,aal.yaml
> index 4fdc9b3283b0..08934b10b54e 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
> +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,aal.yaml
> @@ -1,22 +1,17 @@
>   # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>   %YAML 1.2
>   ---
> -$id: http://devicetree.org/schemas/display/mediatek/mediatek,aal.yaml#
> +$id: http://devicetree.org/schemas/soc/mediatek/mediatek,aal.yaml#
>   $schema: http://devicetree.org/meta-schemas/core.yaml#
>   
> -title: Mediatek display adaptive ambient light processor
> +title: Mediatek adaptive ambient light processor
>   
>   maintainers:
> -  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> -  - Philipp Zabel <p.zabel@pengutronix.de>
> +  - Matthias Brugger <matthias.bgg@gmail.com>
>   
>   description: |
> -  Mediatek display adaptive ambient light processor, namely AAL,
> +  Mediatek adaptive ambient light processor, namely AAL,
>     is responsible for backlight power saving and sunlight visibility improving.
> -  AAL device node must be siblings to the central MMSYS_CONFIG node.
> -  For a description of the MMSYS_CONFIG binding, see
> -  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> -  for details.
>   
>   properties:
>     compatible:
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml
> similarity index 80%
> rename from Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
> rename to Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml
> index 0ed53b6238f0..bf52b7b53475 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
> +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml
> @@ -1,22 +1,17 @@
>   # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>   %YAML 1.2
>   ---
> -$id: http://devicetree.org/schemas/display/mediatek/mediatek,ccorr.yaml#
> +$id: http://devicetree.org/schemas/soc/mediatek/mediatek,ccorr.yaml#
>   $schema: http://devicetree.org/meta-schemas/core.yaml#
>   
> -title: Mediatek display color correction
> +title: Mediatek color correction
>   
>   maintainers:
> -  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> -  - Philipp Zabel <p.zabel@pengutronix.de>
> +  - Matthias Brugger <matthias.bgg@gmail.com>
>   
>   description: |
> -  Mediatek display color correction, namely CCORR, reproduces correct color
> +  Mediatek color correction, namely CCORR, reproduces correct color
>     on panels with different color gamut.
> -  CCORR device node must be siblings to the central MMSYS_CONFIG node.
> -  For a description of the MMSYS_CONFIG binding, see
> -  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> -  for details.
>   
>   properties:
>     compatible:
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,color.yaml
> similarity index 83%
> rename from Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
> rename to Documentation/devicetree/bindings/soc/mediatek/mediatek,color.yaml
> index 3ad842eb5668..91ff2adcf390 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
> +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,color.yaml
> @@ -1,23 +1,18 @@
>   # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>   %YAML 1.2
>   ---
> -$id: http://devicetree.org/schemas/display/mediatek/mediatek,color.yaml#
> +$id: http://devicetree.org/schemas/soc/mediatek/mediatek,color.yaml#
>   $schema: http://devicetree.org/meta-schemas/core.yaml#
>   
> -title: Mediatek display color processor
> +title: Mediatek color processor
>   
>   maintainers:
> -  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> -  - Philipp Zabel <p.zabel@pengutronix.de>
> +  - Matthias Brugger <matthias.bgg@gmail.com>
>   
>   description: |
> -  Mediatek display color processor, namely COLOR, provides hue, luma and
> +  Mediatek color processor, namely COLOR, provides hue, luma and
>     saturation adjustments to get better picture quality and to have one panel
>     resemble the other in their output characteristics.
> -  COLOR device node must be siblings to the central MMSYS_CONFIG node.
> -  For a description of the MMSYS_CONFIG binding, see
> -  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> -  for details.
>   
>   properties:
>     compatible:
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
> similarity index 82%
> rename from Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
> rename to Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
> index 00e6a1041a9b..d334050105db 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
> +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
> @@ -1,25 +1,19 @@
>   # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>   %YAML 1.2
>   ---
> -$id: http://devicetree.org/schemas/display/mediatek/mediatek,mutex.yaml#
> +$id: http://devicetree.org/schemas/soc/mediatek/mediatek,mutex.yaml#
>   $schema: http://devicetree.org/meta-schemas/core.yaml#
>   
>   title: Mediatek mutex
>   
>   maintainers:
> -  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> -  - Philipp Zabel <p.zabel@pengutronix.de>
> +  - Matthias Brugger <matthias.bgg@gmail.com>
>   
>   description: |
>     Mediatek mutex, namely MUTEX, is used to send the triggers signals called
> -  Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display
> -  data path or MDP data path.
> +  Start Of Frame(SOF) / End Of Frame(EOF) to each sub-modules on the data path.
>     In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects
>     the shadow register.
> -  MUTEX device node must be siblings to the central MMSYS_CONFIG node.
> -  For a description of the MMSYS_CONFIG binding, see
> -  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> -  for details.
>   
>   properties:
>     compatible:
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
> similarity index 85%
> rename from Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
> rename to Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
> index 7d7cc1ab526b..a6f9e1b3268d 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
> +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
> @@ -1,22 +1,17 @@
>   # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>   %YAML 1.2
>   ---
> -$id: http://devicetree.org/schemas/display/mediatek/mediatek,wdma.yaml#
> +$id: http://devicetree.org/schemas/soc/mediatek/mediatek,wdma.yaml#
>   $schema: http://devicetree.org/meta-schemas/core.yaml#
>   
>   title: Mediatek Write Direct Memory Access
>   
>   maintainers:
> -  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> -  - Philipp Zabel <p.zabel@pengutronix.de>
> +  - Matthias Brugger <matthias.bgg@gmail.com>
>   
>   description: |
>     Mediatek Write Direct Memory Access(WDMA) component used to write
>     the data into DMA.
> -  WDMA device node must be siblings to the central MMSYS_CONFIG node.
> -  For a description of the MMSYS_CONFIG binding, see
> -  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> -  for details.
>   
>   properties:
>     compatible:

Re: [PATCH v16 2/8] dt-bindings: arm: mediatek: mmsys: add power and gce properties

[AngeloGioacchino Del Regno]

Il 07/03/22 04:28, jason-jh.lin ha scritto:
> Power:
> 1. Add description for power-domains property.
> 
> GCE:
> 1. Add description for mboxes property.
> 2. Add description for mediatek,gce-client-reg property.
> 
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Re: [PATCH v16 3/8] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding

[Jason-JH Lin]

Hi CK,

Thanks for the reviews.

On Fri, 2022-03-18 at 14:43 +0800, CK Hu wrote:
> Hi, Jason:
> 
> On Mon, 2022-03-07 at 11:28 +0800, jason-jh.lin wrote:
> > There are 2 mmsys, namely vdosys0 and vdosys1 in mt8195.
> > Each of them is bound to a display pipeline, so add their
> > definition in mtk-mmsys documentation with 2 compatibles.
> 
> Could one vdosys be union of vdosys0 and vdosys1? In MT8173, one
> mmsys
> support multiple pipeline. Describe more in commit message to support
> that two vdosys are necessary.
> 
> Regards,
> CK
> 

In the SoC before, such as mt8173, it has 2 pipelines binding to one
mmsys with the same clock driver and the same power domain.

In mt8195, 2 pipelines are binding to different mmsys, such as vdosys0
and vdosys1. Each mmsys uses different clock drivers and different
power domain.

Since each mmsys has its own clock, I have tried to differentiate
vppsys0, vppsys1, vdosys0, vdosys1 by the clock names.
Then I can use one mmsys compatible name for all of them.

I'll apply this method at the next version.
And also sync with Nancy(vdosys1) and Roy(vppsys0, vppsys1).

Regards,
Jason-JH.Lin

> > 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> >  .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml        |
> > 2
> > ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git
> > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam
> > l
> > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam
> > l
> > index 6c2c3edcd443..c5ba515cb0d7 100644
> > ---
> > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam
> > l
> > +++
> > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam
> > l
> > @@ -32,6 +32,8 @@ properties:
> >                - mediatek,mt8186-mmsys
> >                - mediatek,mt8192-mmsys
> >                - mediatek,mt8365-mmsys
> > +              - mediatek,mt8195-vdosys0
> > +              - mediatek,mt8195-vdosys1
> >            - const: syscon
> >        - items:
> >            - const: mediatek,mt7623-mmsys
> 
> 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>

Re: [PATCH v16 4/8] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0

[CK Hu]

Hi, Jason:

On Mon, 2022-03-28 at 13:03 +0800, Jason-JH Lin wrote:
> Hi CK,
> 
> Thanks for the reviews.
> 
> On Mon, 2022-03-07 at 11:28 +0800, jason-jh.lin wrote:
> > Add mt8195 vdosys0 clock driver name and routing table to
> > the driver data of mtk-mmsys.
> > 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > Acked-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> > Impelmentation patch of vdosys1 can be refered to [1]
> > 
> > [1] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
> > ---
> >  drivers/soc/mediatek/mt8195-mmsys.h    | 130
> > +++++++++++++++++++++++++
> >  drivers/soc/mediatek/mtk-mmsys.c       |  11 +++
> >  include/linux/soc/mediatek/mtk-mmsys.h |   9 ++
> >  3 files changed, 150 insertions(+)
> >  create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> > 
> > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > b/drivers/soc/mediatek/mt8195-mmsys.h
> > new file mode 100644
> > index 000000000000..24a3afe23bc8
> > --- /dev/null
> > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > @@ -0,0 +1,130 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +
> > +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
> > +#define __SOC_MEDIATEK_MT8195_MMSYS_H
> > +
> > +#define MT8195_VDO0_OVL_MOUT_EN					
> > 0xf14
> > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0			
> > BIT(0)
> > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0			
> > BIT(1)
> >  
> > Useless, so remove.
> > 
> > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1			BIT(2)
> > Ditto.Useless, so remove.
> > Regards,
> > CK
> 
> Although these definitions are not used, they represent the
> functionality provided by this register.
> 
> I think we can show that we have these capabilities by defining them.
> 
> Can we keep these definitions?

It's better that we know how to use it. Even though the symbol name
show some information, but I would like to add it to
mmsys_mt8195_routing_table[].

Regards,
CK

> 
> Regards,
> Jason-JH.Lin
> 
> > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1			
> > BIT(4)
> > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1			
> > BIT(5)
> > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0			BIT(6)
> 
> 
> [snip]
> 

Re: [PATCH v16 4/8] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0

[Jason-JH Lin]

Hi CK,

Thanks for the review.

On Mon, 2022-03-28 at 13:39 +0800, CK Hu wrote:
> Hi, Jason:
> 
> On Mon, 2022-03-28 at 13:03 +0800, Jason-JH Lin wrote:
> > Hi CK,
> > 
> > Thanks for the reviews.
> > 
> > On Mon, 2022-03-07 at 11:28 +0800, jason-jh.lin wrote:
> > > Add mt8195 vdosys0 clock driver name and routing table to
> > > the driver data of mtk-mmsys.
> > > 
> > > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > > Acked-by: AngeloGioacchino Del Regno <
> > > angelogioacchino.delregno@collabora.com>
> > > ---
> > > Impelmentation patch of vdosys1 can be refered to [1]
> > > 
> > > [1] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
> > > ---
> > >  drivers/soc/mediatek/mt8195-mmsys.h    | 130
> > > +++++++++++++++++++++++++
> > >  drivers/soc/mediatek/mtk-mmsys.c       |  11 +++
> > >  include/linux/soc/mediatek/mtk-mmsys.h |   9 ++
> > >  3 files changed, 150 insertions(+)
> > >  create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> > > 
> > > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > > b/drivers/soc/mediatek/mt8195-mmsys.h
> > > new file mode 100644
> > > index 000000000000..24a3afe23bc8
> > > --- /dev/null
> > > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > > @@ -0,0 +1,130 @@
> > > +/* SPDX-License-Identifier: GPL-2.0-only */
> > > +
> > > +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
> > > +#define __SOC_MEDIATEK_MT8195_MMSYS_H
> > > +
> > > +#define MT8195_VDO0_OVL_MOUT_EN					
> > > 0xf14
> > > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0			
> > > BIT(0)
> > > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0			
> > > BIT(1)
> > >  
> > > Useless, so remove.
> > > 
> > > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1			
> > > BIT(2)
> > > Ditto.Useless, so remove.
> > > Regards,
> > > CK
> > 
> > Although these definitions are not used, they represent the
> > functionality provided by this register.
> > 
> > I think we can show that we have these capabilities by defining
> > them.
> > 
> > Can we keep these definitions?
> 
> It's better that we know how to use it. Even though the symbol name
> show some information, but I would like to add it to
> mmsys_mt8195_routing_table[].
> 
> Regards,
> CK
> 

OK, I think I just remove the useless define.
Thanks.

Regards,
Jason-JH.Lin
> > 
> > Regards,
> > Jason-JH.Lin
> > 
> > > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1			
> > > BIT(4)
> > > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1			
> > > BIT(5)
> > > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0			
> > > BIT(6)
> > 
> > 
> > [snip]
> > 
> 
> 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>

Re: [PATCH v16 5/8] soc: mediatek: add mtk-mutex support for mt8195 vdosys0

[Jason-JH Lin]

Hi CK,

Thanks for the reviews.

On Fri, 2022-03-18 at 15:21 +0800, CK Hu wrote:
> Hi, Jason:
> 
> On Mon, 2022-03-07 at 11:28 +0800, jason-jh.lin wrote:
> > Add mtk-mutex support for mt8195 vdosys0.
> > 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > Acked-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> >  drivers/soc/mediatek/mtk-mutex.c | 103
> > ++++++++++++++++++++++++++++++-
> >  1 file changed, 100 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/soc/mediatek/mtk-mutex.c
> > b/drivers/soc/mediatek/mtk-mutex.c
> > index aaf8fc1abb43..1c7ffcdadcea 100644
> > --- a/drivers/soc/mediatek/mtk-mutex.c
> > +++ b/drivers/soc/mediatek/mtk-mutex.c
> > @@ -17,6 +17,9 @@
> >  #define MT8183_MUTEX0_MOD0			0x30
> >  #define MT8183_MUTEX0_SOF0			0x2c
> >  
> > +#define MT8195_DISP_MUTEX0_MOD0			0x30
> > +#define MT8195_DISP_MUTEX0_SOF			0x2c
> > +
> >  #define DISP_REG_MUTEX_EN(n)			(0x20 + 0x20 *
> > (n))
> >  #define DISP_REG_MUTEX(n)			(0x24 + 0x20 * (n))
> >  #define DISP_REG_MUTEX_RST(n)			(0x28 + 0x20 *
> > (n))
> > @@ -96,6 +99,36 @@
> >  #define MT8173_MUTEX_MOD_DISP_PWM1		24
> >  #define MT8173_MUTEX_MOD_DISP_OD		25
> >  

[snip]

> > > +#define MT8195_MUTEX_MOD_DISP_VPP_MERGE		20
> > > +#define MT8195_MUTEX_MOD_DISP_DP_INTF0		21
> > > +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0	22
> > > 
> > > Useless, remove.
> > > 
> > > > +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1	23
> > > 
> > > Ditto.
> > > 
> > > Regards,
> > > CK
> > 
> > Although these definitions are not used, they represent the
> > functionality provided by this register.
> > 
> > I think we can show that we have these capabilities by defining
> them.
> > 
> > Can we keep these definitions?
> 
> OK, but add some information that we could know how to use it. What's
> these DL_RELAY and when should we add these to mutex?
> 
> Regards,
> CK

DL_RELAY is used for the cross mmsys mux settings.
We won't use these setting currently, so I think
I just remove these useless define.

Thanks.

Regards,
Jason-JH.Lin


[snip]

-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>

Re: [PATCH v16 4/8] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0

[Matthias Brugger]

On 30/03/2022 12:04, Jason-JH Lin wrote:
> Hi CK,
> 
> Thanks for the review.
> 
> On Mon, 2022-03-28 at 13:39 +0800, CK Hu wrote:
>> Hi, Jason:
>>
>> On Mon, 2022-03-28 at 13:03 +0800, Jason-JH Lin wrote:
>>> Hi CK,
>>>
>>> Thanks for the reviews.
>>>
>>> On Mon, 2022-03-07 at 11:28 +0800, jason-jh.lin wrote:
>>>> Add mt8195 vdosys0 clock driver name and routing table to
>>>> the driver data of mtk-mmsys.
>>>>
>>>> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
>>>> Acked-by: AngeloGioacchino Del Regno <
>>>> angelogioacchino.delregno@collabora.com>
>>>> ---
>>>> Impelmentation patch of vdosys1 can be refered to [1]
>>>>
>>>> [1] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
>>>> ---
>>>>   drivers/soc/mediatek/mt8195-mmsys.h    | 130
>>>> +++++++++++++++++++++++++
>>>>   drivers/soc/mediatek/mtk-mmsys.c       |  11 +++
>>>>   include/linux/soc/mediatek/mtk-mmsys.h |   9 ++
>>>>   3 files changed, 150 insertions(+)
>>>>   create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
>>>>
>>>> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
>>>> b/drivers/soc/mediatek/mt8195-mmsys.h
>>>> new file mode 100644
>>>> index 000000000000..24a3afe23bc8
>>>> --- /dev/null
>>>> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
>>>> @@ -0,0 +1,130 @@
>>>> +/* SPDX-License-Identifier: GPL-2.0-only */
>>>> +
>>>> +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
>>>> +#define __SOC_MEDIATEK_MT8195_MMSYS_H
>>>> +
>>>> +#define MT8195_VDO0_OVL_MOUT_EN					
>>>> 0xf14
>>>> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0			
>>>> BIT(0)
>>>> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0			
>>>> BIT(1)
>>>>   
>>>> Useless, so remove.
>>>>
>>>> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1			
>>>> BIT(2)
>>>> Ditto.Useless, so remove.
>>>> Regards,
>>>> CK
>>>
>>> Although these definitions are not used, they represent the
>>> functionality provided by this register.
>>>
>>> I think we can show that we have these capabilities by defining
>>> them.
>>>
>>> Can we keep these definitions?
>>
>> It's better that we know how to use it. Even though the symbol name
>> show some information, but I would like to add it to
>> mmsys_mt8195_routing_table[].
>>
>> Regards,
>> CK
>>
> 
> OK, I think I just remove the useless define.

Actually I would prefer to add it to the routing table to describe all the 
capabilities of the HW.

Is there any technical problem with that?

Regards,
Matthias

> Thanks.
> 
> Regards,
> Jason-JH.Lin
>>>
>>> Regards,
>>> Jason-JH.Lin
>>>
>>>> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1			
>>>> BIT(4)
>>>> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1			
>>>> BIT(5)
>>>> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0			
>>>> BIT(6)
>>>
>>>
>>> [snip]
>>>
>>
>>

Re: [PATCH v16 2/8] dt-bindings: arm: mediatek: mmsys: add power and gce properties

[Matthias Brugger]

On 07/03/2022 04:28, jason-jh.lin wrote:
> Power:
> 1. Add description for power-domains property.
> 
> GCE:
> 1. Add description for mboxes property.
> 2. Add description for mediatek,gce-client-reg property.
> 

As you have to resend the series anyway, would you mind to make the commit 
message more sound with whole phrases? Other then that, the patch looks good.

Thanks,
Matthias

> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
>   .../bindings/arm/mediatek/mediatek,mmsys.yaml | 31 +++++++++++++++++++
>   1 file changed, 31 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> index b31d90dc9eb4..6c2c3edcd443 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> @@ -41,6 +41,30 @@ properties:
>     reg:
>       maxItems: 1
>   
> +  power-domains:
> +    description:
> +      A phandle and PM domain specifier as defined by bindings
> +      of the power controller specified by phandle. See
> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> +  mboxes:
> +    description:
> +      Using mailbox to communicate with GCE, it should have this
> +      property and list of phandle, mailbox specifiers. See
> +      Documentation/devicetree/bindings/mailbox/mtk-gce.txt for details.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +
> +  mediatek,gce-client-reg:
> +    description:
> +      The register of client driver can be configured by gce with 4 arguments
> +      defined in this property, such as phandle of gce, subsys id,
> +      register offset and size.
> +      Each subsys id is mapping to a base address of display function blocks
> +      register which is defined in the gce header
> +      include/dt-bindings/gce/<chip>-gce.h.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    maxItems: 1
> +
>     "#clock-cells":
>       const: 1
>   
> @@ -56,9 +80,16 @@ additionalProperties: false
>   
>   examples:
>     - |
> +    #include <dt-bindings/power/mt8173-power.h>
> +    #include <dt-bindings/gce/mt8173-gce.h>
> +
>       mmsys: syscon@14000000 {
>           compatible = "mediatek,mt8173-mmsys", "syscon";
>           reg = <0x14000000 0x1000>;
> +        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
>           #clock-cells = <1>;
>           #reset-cells = <1>;
> +        mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
> +                 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
> +        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
>       };

Re: [PATCH v16 4/8] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0

[Jason-JH Lin]

Hi Matthias,

 * Thanks for the reviews.

On Thu, 2022-03-31 at 13:01 +0200, Matthias Brugger wrote:
> 
> On 30/03/2022 12:04, Jason-JH Lin wrote:
> > Hi CK,
> > 
> > Thanks for the review.
> > 
> > On Mon, 2022-03-28 at 13:39 +0800, CK Hu wrote:
> > > Hi, Jason:
> > > 
> > > On Mon, 2022-03-28 at 13:03 +0800, Jason-JH Lin wrote:
> > > > Hi CK,
> > > > 
> > > > Thanks for the reviews.
> > > > 
> > > > On Mon, 2022-03-07 at 11:28 +0800, jason-jh.lin wrote:
> > > > > Add mt8195 vdosys0 clock driver name and routing table to
> > > > > the driver data of mtk-mmsys.
> > > > > 
> > > > > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > > > > Acked-by: AngeloGioacchino Del Regno <
> > > > > angelogioacchino.delregno@collabora.com>
> > > > > ---
> > > > > Impelmentation patch of vdosys1 can be refered to [1]
> > > > > 
> > > > > [1] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
> > > > > ---
> > > > >   drivers/soc/mediatek/mt8195-mmsys.h    | 130
> > > > > +++++++++++++++++++++++++
> > > > >   drivers/soc/mediatek/mtk-mmsys.c       |  11 +++
> > > > >   include/linux/soc/mediatek/mtk-mmsys.h |   9 ++
> > > > >   3 files changed, 150 insertions(+)
> > > > >   create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> > > > > 
> > > > > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > > > > b/drivers/soc/mediatek/mt8195-mmsys.h
> > > > > new file mode 100644
> > > > > index 000000000000..24a3afe23bc8
> > > > > --- /dev/null
> > > > > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > > > > @@ -0,0 +1,130 @@
> > > > > +/* SPDX-License-Identifier: GPL-2.0-only */
> > > > > +
> > > > > +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
> > > > > +#define __SOC_MEDIATEK_MT8195_MMSYS_H
> > > > > +
> > > > > +#define MT8195_VDO0_OVL_MOUT_EN				
> > > > > 	
> > > > > 0xf14
> > > > > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0			
> > > > > BIT(0)
> > > > > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0			
> > > > > BIT(1)
> > > > >   
> > > > > Useless, so remove.
> > > > > 
> > > > > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1			
> > > > > BIT(2)
> > > > > Ditto.Useless, so remove.
> > > > > Regards,
> > > > > CK
> > > > 
> > > > Although these definitions are not used, they represent the
> > > > functionality provided by this register.
> > > > 
> > > > I think we can show that we have these capabilities by defining
> > > > them.
> > > > 
> > > > Can we keep these definitions?
> > > 
> > > It's better that we know how to use it. Even though the symbol
> > > name
> > > show some information, but I would like to add it to
> > > mmsys_mt8195_routing_table[].
> > > 
> > > Regards,
> > > CK
> > > 
> > 
> > OK, I think I just remove the useless define.
> 
> Actually I would prefer to add it to the routing table to describe
> all the 
> capabilities of the HW.
> 
> Is there any technical problem with that?
> 
> Regards,
> Matthias
> 
OK, I'll add keep these definitions and add them to the routing table.

Regards,
Jason-JH.Lin

> > Thanks.
> > 
> > Regards,
> > Jason-JH.Lin
> > > > 
> > > > Regards,
> > > > Jason-JH.Lin
> > > > 
> > > > > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1			
> > > > > BIT(4)
> > > > > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1			
> > > > > BIT(5)
> > > > > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0			
> > > > > BIT(6)
> > > > 
> > > > 
> > > > [snip]
> > > > 
> > > 
> > > 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>