* [PATCH v2 0/2] Add DSS support for TI AM62A7 SoC @ 2023-08-18 14:21 Aradhya Bhatia 2023-08-18 14:21 ` [PATCH v2 1/2] dt-bindings: display: ti: Add support for am62a7 dss Aradhya Bhatia 2023-08-18 14:21 ` [PATCH v2 2/2] drivers/tidss: Add support for AM62A7 DSS Aradhya Bhatia 0 siblings, 2 replies; 5+ messages in thread From: Aradhya Bhatia @ 2023-08-18 14:21 UTC (permalink / raw) To: Tomi Valkeinen, Jyri Sarha, David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: DRI Development List, Devicetree List, Linux Kernel List, Nishanth Menon, Vignesh Raghavendra, Devarsh Thakkar, Jayesh Choudhary, Jai Luthra, Aradhya Bhatia This patch series adds a new compatible for the Display SubSystem (DSS) controller on TI's AM62A7 SoC. It further adds the required support, for the same, in the tidss driver. The DSS controller is similar to the recently added AM625 DSS, with the key difference being the absence of VP1 output on the SoC. The VP1 in AM62A7 DSS is tied off and cannot be used, unlike in AM625, where the VP1 was connected to 2 OLDI TXes. The video pipeline that corresponds to VP1 still exists and can be used to overlay planes on the VP2's primary plane. This can be done using the overlay managers inside the SoC. Moreover, DSS VP2 can output Full-HD RGB888 DPI video signals. I have tested these patches on AM62A7 SK-EVM, which converts DPI signals to HDMI on the platform using the Sil9022A HDMI transmitter. All the patches, required to enable display on AM62A7-SK, can be found on my github fork[0] in the branch "next_am62a-v2". Regards Aradhya [0]: https://github.com/aradhya07/linux-ab/tree/next_am62a-v2 Change Log: V1 -> V2: - Correctly sort DISPC_AM62A7 macro after DISPC_AM625 in patch 2/2. Previous Versions: V1: https://lore.kernel.org/all/20230818131750.4779-1-a-bhatia1@ti.com/ Aradhya Bhatia (2): dt-bindings: display: ti: Add support for am62a7 dss drivers/tidss: Add support for AM62A7 DSS .../bindings/display/ti/ti,am65x-dss.yaml | 14 +++++ drivers/gpu/drm/tidss/tidss_dispc.c | 53 +++++++++++++++++++ drivers/gpu/drm/tidss/tidss_dispc.h | 2 + drivers/gpu/drm/tidss/tidss_drv.c | 1 + 4 files changed, 70 insertions(+) base-commit: 47762f08697484cf0c2f2904b8c52375ed26c8cb -- 2.40.1 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 1/2] dt-bindings: display: ti: Add support for am62a7 dss 2023-08-18 14:21 [PATCH v2 0/2] Add DSS support for TI AM62A7 SoC Aradhya Bhatia @ 2023-08-18 14:21 ` Aradhya Bhatia 2023-08-19 12:51 ` Krzysztof Kozlowski 2023-08-18 14:21 ` [PATCH v2 2/2] drivers/tidss: Add support for AM62A7 DSS Aradhya Bhatia 1 sibling, 1 reply; 5+ messages in thread From: Aradhya Bhatia @ 2023-08-18 14:21 UTC (permalink / raw) To: Tomi Valkeinen, Jyri Sarha, David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: DRI Development List, Devicetree List, Linux Kernel List, Nishanth Menon, Vignesh Raghavendra, Devarsh Thakkar, Jayesh Choudhary, Jai Luthra, Aradhya Bhatia The DSS controller on TI's AM62A7 SoC is an update from that on TI's AM625 SoC. Like the DSS in AM625, the DSS in this SoC has 2 video pipelines, but unlike the former, the latter only has one output port on VP2 to service DPI display sinks. Add the new controller's compatible. Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com> --- Notes: Changes from V1: * No change from V1. .../bindings/display/ti/ti,am65x-dss.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml index ae09cd3cbce1..b6767ef0d24d 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml @@ -23,6 +23,7 @@ properties: compatible: enum: - ti,am625-dss + - ti,am62a7,dss - ti,am65x-dss reg: @@ -87,6 +88,7 @@ properties: For AM65x DSS, the OLDI output port node from video port 1. For AM625 DSS, the internal DPI output port node from video port 1. + For AM62A7 DSS, the port is tied off inside the SoC. port@1: $ref: /schemas/graph.yaml#/properties/port @@ -108,6 +110,18 @@ properties: Input memory (from main memory to dispc) bandwidth limit in bytes per second +allOf: + - if: + properties: + compatible: + contains: + const: ti,am62a7-dss + then: + properties: + ports: + properties: + port@0: false + required: - compatible - reg -- 2.40.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2 1/2] dt-bindings: display: ti: Add support for am62a7 dss 2023-08-18 14:21 ` [PATCH v2 1/2] dt-bindings: display: ti: Add support for am62a7 dss Aradhya Bhatia @ 2023-08-19 12:51 ` Krzysztof Kozlowski 0 siblings, 0 replies; 5+ messages in thread From: Krzysztof Kozlowski @ 2023-08-19 12:51 UTC (permalink / raw) To: Aradhya Bhatia, Tomi Valkeinen, Jyri Sarha, David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: DRI Development List, Devicetree List, Linux Kernel List, Nishanth Menon, Vignesh Raghavendra, Devarsh Thakkar, Jayesh Choudhary, Jai Luthra On 18/08/2023 16:21, Aradhya Bhatia wrote: > The DSS controller on TI's AM62A7 SoC is an update from that on TI's > AM625 SoC. Like the DSS in AM625, the DSS in this SoC has 2 video > pipelines, but unlike the former, the latter only has one output port on > VP2 to service DPI display sinks. > > Add the new controller's compatible. > > Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com> > --- Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 2/2] drivers/tidss: Add support for AM62A7 DSS 2023-08-18 14:21 [PATCH v2 0/2] Add DSS support for TI AM62A7 SoC Aradhya Bhatia 2023-08-18 14:21 ` [PATCH v2 1/2] dt-bindings: display: ti: Add support for am62a7 dss Aradhya Bhatia @ 2023-08-18 14:21 ` Aradhya Bhatia 2023-09-18 15:23 ` Tomi Valkeinen 1 sibling, 1 reply; 5+ messages in thread From: Aradhya Bhatia @ 2023-08-18 14:21 UTC (permalink / raw) To: Tomi Valkeinen, Jyri Sarha, David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: DRI Development List, Devicetree List, Linux Kernel List, Nishanth Menon, Vignesh Raghavendra, Devarsh Thakkar, Jayesh Choudhary, Jai Luthra, Aradhya Bhatia Add support for the DSS controller on TI's AM62A7 SoC in the tidss driver. This contrller has 2 video pipelines that can render 2 video planes on over a screen, using the overlay managers. The output of the DSS comes from video port 2 (VP2) in the form of RGB88 DPI signals, while the VP1 is tied off inside the SoC. Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com> --- Notes: Changes from V1: * Correctly sort DISPC_AM62A7 macro after DISPC_AM625. drivers/gpu/drm/tidss/tidss_dispc.c | 53 +++++++++++++++++++++++++++++ drivers/gpu/drm/tidss/tidss_dispc.h | 2 ++ drivers/gpu/drm/tidss/tidss_drv.c | 1 + 3 files changed, 56 insertions(+) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c index 9d9dee7abaef..5539ddb7f338 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -322,6 +322,54 @@ const struct dispc_features dispc_am625_feats = { .vid_order = { 1, 0 }, }; +const struct dispc_features dispc_am62a7_feats = { + .max_pclk_khz = { + [DISPC_VP_DPI] = 165000, + }, + + .scaling = { + .in_width_max_5tap_rgb = 1280, + .in_width_max_3tap_rgb = 2560, + .in_width_max_5tap_yuv = 2560, + .in_width_max_3tap_yuv = 4096, + .upscale_limit = 16, + .downscale_limit_5tap = 4, + .downscale_limit_3tap = 2, + /* + * The max supported pixel inc value is 255. The value + * of pixel inc is calculated like this: 1+(xinc-1)*bpp. + * The maximum bpp of all formats supported by the HW + * is 8. So the maximum supported xinc value is 32, + * because 1+(32-1)*8 < 255 < 1+(33-1)*4. + */ + .xinc_max = 32, + }, + + .subrev = DISPC_AM62A7, + + .common = "common", + .common_regs = tidss_am65x_common_regs, + + .num_vps = 2, + .vp_name = { "vp1", "vp2" }, + .ovr_name = { "ovr1", "ovr2" }, + .vpclk_name = { "vp1", "vp2" }, + .vp_bus_type = { DISPC_VP_INTERNAL, DISPC_VP_DPI }, + + .vp_feat = { .color = { + .has_ctm = true, + .gamma_size = 256, + .gamma_type = TIDSS_GAMMA_8BIT, + }, + }, + + .num_planes = 2, + /* note: vid is plane_id 0 and vidl1 is plane_id 1 */ + .vid_name = { "vid", "vidl1" }, + .vid_lite = { false, true, }, + .vid_order = { 1, 0 }, +}; + static const u16 *dispc_common_regmap; struct dss_vp_data { @@ -824,6 +872,7 @@ dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc) case DISPC_K2G: return dispc_k2g_read_and_clear_irqstatus(dispc); case DISPC_AM625: + case DISPC_AM62A7: case DISPC_AM65X: case DISPC_J721E: return dispc_k3_read_and_clear_irqstatus(dispc); @@ -840,6 +889,7 @@ void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask) dispc_k2g_set_irqenable(dispc, mask); break; case DISPC_AM625: + case DISPC_AM62A7: case DISPC_AM65X: case DISPC_J721E: dispc_k3_set_irqenable(dispc, mask); @@ -1331,6 +1381,7 @@ void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, x, y, layer); break; case DISPC_AM625: + case DISPC_AM62A7: case DISPC_AM65X: dispc_am65x_ovr_set_plane(dispc, hw_plane, hw_videoport, x, y, layer); @@ -2250,6 +2301,7 @@ static void dispc_plane_init(struct dispc_device *dispc) dispc_k2g_plane_init(dispc); break; case DISPC_AM625: + case DISPC_AM62A7: case DISPC_AM65X: case DISPC_J721E: dispc_k3_plane_init(dispc); @@ -2357,6 +2409,7 @@ static void dispc_vp_write_gamma_table(struct dispc_device *dispc, dispc_k2g_vp_write_gamma_table(dispc, hw_videoport); break; case DISPC_AM625: + case DISPC_AM62A7: case DISPC_AM65X: dispc_am65x_vp_write_gamma_table(dispc, hw_videoport); break; diff --git a/drivers/gpu/drm/tidss/tidss_dispc.h b/drivers/gpu/drm/tidss/tidss_dispc.h index 33ac5ad7a423..7f203f83559b 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.h +++ b/drivers/gpu/drm/tidss/tidss_dispc.h @@ -60,6 +60,7 @@ enum dispc_vp_bus_type { enum dispc_dss_subrevision { DISPC_K2G, DISPC_AM625, + DISPC_AM62A7, DISPC_AM65X, DISPC_J721E, }; @@ -88,6 +89,7 @@ struct dispc_features { extern const struct dispc_features dispc_k2g_feats; extern const struct dispc_features dispc_am625_feats; +extern const struct dispc_features dispc_am62a7_feats; extern const struct dispc_features dispc_am65x_feats; extern const struct dispc_features dispc_j721e_feats; diff --git a/drivers/gpu/drm/tidss/tidss_drv.c b/drivers/gpu/drm/tidss/tidss_drv.c index 4d063eb9cd0b..edf69d020544 100644 --- a/drivers/gpu/drm/tidss/tidss_drv.c +++ b/drivers/gpu/drm/tidss/tidss_drv.c @@ -231,6 +231,7 @@ static void tidss_shutdown(struct platform_device *pdev) static const struct of_device_id tidss_of_table[] = { { .compatible = "ti,k2g-dss", .data = &dispc_k2g_feats, }, { .compatible = "ti,am625-dss", .data = &dispc_am625_feats, }, + { .compatible = "ti,am62a7-dss", .data = &dispc_am62a7_feats, }, { .compatible = "ti,am65x-dss", .data = &dispc_am65x_feats, }, { .compatible = "ti,j721e-dss", .data = &dispc_j721e_feats, }, { } -- 2.40.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2 2/2] drivers/tidss: Add support for AM62A7 DSS 2023-08-18 14:21 ` [PATCH v2 2/2] drivers/tidss: Add support for AM62A7 DSS Aradhya Bhatia @ 2023-09-18 15:23 ` Tomi Valkeinen 0 siblings, 0 replies; 5+ messages in thread From: Tomi Valkeinen @ 2023-09-18 15:23 UTC (permalink / raw) To: Aradhya Bhatia, Jyri Sarha, David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: DRI Development List, Devicetree List, Linux Kernel List, Nishanth Menon, Vignesh Raghavendra, Devarsh Thakkar, Jayesh Choudhary, Jai Luthra On 18/08/2023 17:21, Aradhya Bhatia wrote: > Add support for the DSS controller on TI's AM62A7 SoC in the tidss > driver. > > This contrller has 2 video pipelines that can render 2 video planes on "controller". > over a screen, using the overlay managers. The output of the DSS comes > from video port 2 (VP2) in the form of RGB88 DPI signals, while the VP1 > is tied off inside the SoC. If the VP1 is tied off, I think we should somehow mark it in the feats below. Maybe just a comment, or perhaps a new DISPC_VP_* flag. Tomi > Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com> > --- > Notes: > Changes from V1: > * Correctly sort DISPC_AM62A7 macro after DISPC_AM625. > > drivers/gpu/drm/tidss/tidss_dispc.c | 53 +++++++++++++++++++++++++++++ > drivers/gpu/drm/tidss/tidss_dispc.h | 2 ++ > drivers/gpu/drm/tidss/tidss_drv.c | 1 + > 3 files changed, 56 insertions(+) > > diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c > index 9d9dee7abaef..5539ddb7f338 100644 > --- a/drivers/gpu/drm/tidss/tidss_dispc.c > +++ b/drivers/gpu/drm/tidss/tidss_dispc.c > @@ -322,6 +322,54 @@ const struct dispc_features dispc_am625_feats = { > .vid_order = { 1, 0 }, > }; > > +const struct dispc_features dispc_am62a7_feats = { > + .max_pclk_khz = { > + [DISPC_VP_DPI] = 165000, > + }, > + > + .scaling = { > + .in_width_max_5tap_rgb = 1280, > + .in_width_max_3tap_rgb = 2560, > + .in_width_max_5tap_yuv = 2560, > + .in_width_max_3tap_yuv = 4096, > + .upscale_limit = 16, > + .downscale_limit_5tap = 4, > + .downscale_limit_3tap = 2, > + /* > + * The max supported pixel inc value is 255. The value > + * of pixel inc is calculated like this: 1+(xinc-1)*bpp. > + * The maximum bpp of all formats supported by the HW > + * is 8. So the maximum supported xinc value is 32, > + * because 1+(32-1)*8 < 255 < 1+(33-1)*4. > + */ > + .xinc_max = 32, > + }, > + > + .subrev = DISPC_AM62A7, > + > + .common = "common", > + .common_regs = tidss_am65x_common_regs, > + > + .num_vps = 2, > + .vp_name = { "vp1", "vp2" }, > + .ovr_name = { "ovr1", "ovr2" }, > + .vpclk_name = { "vp1", "vp2" }, > + .vp_bus_type = { DISPC_VP_INTERNAL, DISPC_VP_DPI }, > + > + .vp_feat = { .color = { > + .has_ctm = true, > + .gamma_size = 256, > + .gamma_type = TIDSS_GAMMA_8BIT, > + }, > + }, > + > + .num_planes = 2, > + /* note: vid is plane_id 0 and vidl1 is plane_id 1 */ > + .vid_name = { "vid", "vidl1" }, > + .vid_lite = { false, true, }, > + .vid_order = { 1, 0 }, > +}; > + > static const u16 *dispc_common_regmap; > > struct dss_vp_data { > @@ -824,6 +872,7 @@ dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc) > case DISPC_K2G: > return dispc_k2g_read_and_clear_irqstatus(dispc); > case DISPC_AM625: > + case DISPC_AM62A7: > case DISPC_AM65X: > case DISPC_J721E: > return dispc_k3_read_and_clear_irqstatus(dispc); > @@ -840,6 +889,7 @@ void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask) > dispc_k2g_set_irqenable(dispc, mask); > break; > case DISPC_AM625: > + case DISPC_AM62A7: > case DISPC_AM65X: > case DISPC_J721E: > dispc_k3_set_irqenable(dispc, mask); > @@ -1331,6 +1381,7 @@ void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, > x, y, layer); > break; > case DISPC_AM625: > + case DISPC_AM62A7: > case DISPC_AM65X: > dispc_am65x_ovr_set_plane(dispc, hw_plane, hw_videoport, > x, y, layer); > @@ -2250,6 +2301,7 @@ static void dispc_plane_init(struct dispc_device *dispc) > dispc_k2g_plane_init(dispc); > break; > case DISPC_AM625: > + case DISPC_AM62A7: > case DISPC_AM65X: > case DISPC_J721E: > dispc_k3_plane_init(dispc); > @@ -2357,6 +2409,7 @@ static void dispc_vp_write_gamma_table(struct dispc_device *dispc, > dispc_k2g_vp_write_gamma_table(dispc, hw_videoport); > break; > case DISPC_AM625: > + case DISPC_AM62A7: > case DISPC_AM65X: > dispc_am65x_vp_write_gamma_table(dispc, hw_videoport); > break; > diff --git a/drivers/gpu/drm/tidss/tidss_dispc.h b/drivers/gpu/drm/tidss/tidss_dispc.h > index 33ac5ad7a423..7f203f83559b 100644 > --- a/drivers/gpu/drm/tidss/tidss_dispc.h > +++ b/drivers/gpu/drm/tidss/tidss_dispc.h > @@ -60,6 +60,7 @@ enum dispc_vp_bus_type { > enum dispc_dss_subrevision { > DISPC_K2G, > DISPC_AM625, > + DISPC_AM62A7, > DISPC_AM65X, > DISPC_J721E, > }; > @@ -88,6 +89,7 @@ struct dispc_features { > > extern const struct dispc_features dispc_k2g_feats; > extern const struct dispc_features dispc_am625_feats; > +extern const struct dispc_features dispc_am62a7_feats; > extern const struct dispc_features dispc_am65x_feats; > extern const struct dispc_features dispc_j721e_feats; > > diff --git a/drivers/gpu/drm/tidss/tidss_drv.c b/drivers/gpu/drm/tidss/tidss_drv.c > index 4d063eb9cd0b..edf69d020544 100644 > --- a/drivers/gpu/drm/tidss/tidss_drv.c > +++ b/drivers/gpu/drm/tidss/tidss_drv.c > @@ -231,6 +231,7 @@ static void tidss_shutdown(struct platform_device *pdev) > static const struct of_device_id tidss_of_table[] = { > { .compatible = "ti,k2g-dss", .data = &dispc_k2g_feats, }, > { .compatible = "ti,am625-dss", .data = &dispc_am625_feats, }, > + { .compatible = "ti,am62a7-dss", .data = &dispc_am62a7_feats, }, > { .compatible = "ti,am65x-dss", .data = &dispc_am65x_feats, }, > { .compatible = "ti,j721e-dss", .data = &dispc_j721e_feats, }, > { } ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-09-18 15:28 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-08-18 14:21 [PATCH v2 0/2] Add DSS support for TI AM62A7 SoC Aradhya Bhatia 2023-08-18 14:21 ` [PATCH v2 1/2] dt-bindings: display: ti: Add support for am62a7 dss Aradhya Bhatia 2023-08-19 12:51 ` Krzysztof Kozlowski 2023-08-18 14:21 ` [PATCH v2 2/2] drivers/tidss: Add support for AM62A7 DSS Aradhya Bhatia 2023-09-18 15:23 ` Tomi Valkeinen
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).