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Fri, 20 Jan 2023 00:38:22 -0800 (PST) Received: from [192.168.1.109] ([178.197.216.144]) by smtp.gmail.com with ESMTPSA id 2-20020a05600c028200b003cf6a55d8e8sm1550522wmk.7.2023.01.20.00.38.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 20 Jan 2023 00:38:22 -0800 (PST) Message-ID: Date: Fri, 20 Jan 2023 09:38:19 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.0 Subject: Re: [PATCH v3 2/2] PCI: qcom: Add SM8550 PCIe support Content-Language: en-US To: Abel Vesa , Andy Gross , Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , Rob Herring , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Linux Kernel Mailing List References: <20230119112453.3393911-1-abel.vesa@linaro.org> <20230119112453.3393911-2-abel.vesa@linaro.org> From: Krzysztof Kozlowski In-Reply-To: <20230119112453.3393911-2-abel.vesa@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 19/01/2023 12:24, Abel Vesa wrote: > Add compatible for both PCIe found on SM8550. > Also add the cnoc_pcie_sf_axi clock needed by the SM8550. > > Signed-off-by: Abel Vesa > Reviewed-by: Konrad Dybcio > --- > > The v2 was here: > https://lore.kernel.org/all/20230118111704.3553542-2-abel.vesa@linaro.org/ > > Changes since v2: > * none > > Changes since v1: > * changed the subject line prefix for the patch to match the history, > like Bjorn Helgaas suggested. > * added Konrad's R-b tag > > > drivers/pci/controller/dwc/pcie-qcom.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 77e5dc7b88ad..85988b3fd4f6 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -182,7 +182,7 @@ struct qcom_pcie_resources_2_3_3 { > > /* 6 clocks typically, 7 for sm8250 */ > struct qcom_pcie_resources_2_7_0 { > - struct clk_bulk_data clks[12]; > + struct clk_bulk_data clks[13]; > int num_clks; > struct regulator_bulk_data supplies[2]; > struct reset_control *pci_reset; > @@ -1208,6 +1208,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) > res->clks[idx++].id = "noc_aggr_4"; > res->clks[idx++].id = "noc_aggr_south_sf"; > res->clks[idx++].id = "cnoc_qx"; > + res->clks[idx++].id = "cnoc_pcie_sf_axi"; > > num_opt_clks = idx - num_clks; > res->num_clks = idx; > @@ -1828,6 +1829,7 @@ static const struct of_device_id qcom_pcie_match[] = { > { .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 }, > { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 }, > { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 }, > + { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 }, This does not match your bindings. Basically, this is very similar to other models but bindings suggest otherwise - several new properties, optional existing properties. Best regards, Krzysztof