From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E64F3C56201 for ; Sat, 28 Nov 2020 04:33:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B723C21534 for ; Sat, 28 Nov 2020 04:33:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732236AbgK1Eb5 (ORCPT ); Fri, 27 Nov 2020 23:31:57 -0500 Received: from szxga08-in.huawei.com ([45.249.212.255]:2317 "EHLO szxga08-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731107AbgK1EbZ (ORCPT ); Fri, 27 Nov 2020 23:31:25 -0500 Received: from dggeme755-chm.china.huawei.com (unknown [172.30.72.53]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4CjdHN68zHz13NCK; Sat, 28 Nov 2020 12:07:12 +0800 (CST) Received: from [10.140.157.68] (10.140.157.68) by dggeme755-chm.china.huawei.com (10.3.19.101) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1913.5; Sat, 28 Nov 2020 12:07:52 +0800 Subject: Re: [PATCH v5 0/4] Enable Hi3559A SOC clock and HiSilicon Hiedma Controller To: , , , , , , , , , References: <20201119200129.28532-1-gengdongjiu@huawei.com> From: Dongjiu Geng Message-ID: Date: Sat, 28 Nov 2020 12:07:51 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: <20201119200129.28532-1-gengdongjiu@huawei.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.140.157.68] X-ClientProxiedBy: dggeme718-chm.china.huawei.com (10.1.199.114) To dggeme755-chm.china.huawei.com (10.3.19.101) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org ping, sorry for the noise. On 2020/11/20 4:01, Dongjiu Geng wrote: > v4->v5: > 1. change the patch author mail name > > v3->v4: > 1. fix the 'make dt_binding_check' issues. > 2. Combine the 'Enable HiSilicon Hiedma Controller' series patches to this series. > 3. fix the 'make dt_binding_check' issues in 'Enable HiSilicon Hiedma Controller' patchset > > > v2->v3: > 1. change dt-bindings documents from txt to yaml format. > 2. Add SHUB clock to access the devices of m7 > > Dongjiu Geng (4): > dt-bindings: Document the hi3559a clock bindings > clk: hisilicon: Add clock driver for hi3559A SoC > dt: bindings: dma: Add DT bindings for HiSilicon Hiedma Controller > dmaengine: dma: Add Hiedma Controller v310 Device Driver > > .../clock/hisilicon,hi3559av100-clock.yaml | 66 + > .../bindings/dma/hisilicon,hiedmacv310.yaml | 103 ++ > drivers/clk/hisilicon/Kconfig | 7 + > drivers/clk/hisilicon/Makefile | 1 + > drivers/clk/hisilicon/clk-hi3559a.c | 865 ++++++++++ > drivers/dma/Kconfig | 14 + > drivers/dma/Makefile | 1 + > drivers/dma/hiedmacv310.c | 1441 +++++++++++++++++ > drivers/dma/hiedmacv310.h | 136 ++ > include/dt-bindings/clock/hi3559av100-clock.h | 165 ++ > 10 files changed, 2799 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/hisilicon,hi3559av100-clock.yaml > create mode 100644 Documentation/devicetree/bindings/dma/hisilicon,hiedmacv310.yaml > create mode 100644 drivers/clk/hisilicon/clk-hi3559a.c > create mode 100644 drivers/dma/hiedmacv310.c > create mode 100644 drivers/dma/hiedmacv310.h > create mode 100644 include/dt-bindings/clock/hi3559av100-clock.h >