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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id q2-20020a056402032200b00423d4516387sm6040085edw.75.2022.04.19.23.54.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 19 Apr 2022 23:54:16 -0700 (PDT) Message-ID: Date: Wed, 20 Apr 2022 08:54:15 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH 3/3] dt-bindings: arm: mediatek: infracfg: Convert to DT schema Content-Language: en-US To: Yassine Oudjana , Rob Herring , Krzysztof Kozlowski , Matthias Brugger Cc: Sam Shih , Stephen Boyd , Ryder Lee , Yassine Oudjana , devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20220419180938.19397-1-y.oudjana@protonmail.com> <20220419180938.19397-4-y.oudjana@protonmail.com> From: Krzysztof Kozlowski In-Reply-To: <20220419180938.19397-4-y.oudjana@protonmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 19/04/2022 20:09, Yassine Oudjana wrote: > From: Yassine Oudjana > > Convert infracfg bindings to DT schema format. Not all drivers > currently implement resets, so #reset-cells is made a required > property only for those that do. Using power-controller in the > example node name makes #power-domain-cells required causing > a dt_binding_check error. To solve this, the node is renamed to > syscon@10001000. > > Signed-off-by: Yassine Oudjana > --- > .../arm/mediatek/mediatek,infracfg.txt | 42 ---------- > .../arm/mediatek/mediatek,infracfg.yaml | 79 +++++++++++++++++++ > 2 files changed, 79 insertions(+), 42 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml > > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt > deleted file mode 100644 > index f66bd720571d..000000000000 > --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt > +++ /dev/null > @@ -1,42 +0,0 @@ > -Mediatek infracfg controller > -============================ > - > -The Mediatek infracfg controller provides various clocks and reset > -outputs to the system. > - > -Required Properties: > - > -- compatible: Should be one of: > - - "mediatek,mt2701-infracfg", "syscon" > - - "mediatek,mt2712-infracfg", "syscon" > - - "mediatek,mt6765-infracfg", "syscon" > - - "mediatek,mt6779-infracfg_ao", "syscon" > - - "mediatek,mt6797-infracfg", "syscon" > - - "mediatek,mt7622-infracfg", "syscon" > - - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon" > - - "mediatek,mt7629-infracfg", "syscon" > - - "mediatek,mt7986-infracfg", "syscon" > - - "mediatek,mt8135-infracfg", "syscon" > - - "mediatek,mt8167-infracfg", "syscon" > - - "mediatek,mt8173-infracfg", "syscon" > - - "mediatek,mt8183-infracfg", "syscon" > - - "mediatek,mt8516-infracfg", "syscon" > -- #clock-cells: Must be 1 > -- #reset-cells: Must be 1 > - > -The infracfg controller uses the common clk binding from > -Documentation/devicetree/bindings/clock/clock-bindings.txt > -The available clocks are defined in dt-bindings/clock/mt*-clk.h. > -Also it uses the common reset controller binding from > -Documentation/devicetree/bindings/reset/reset.txt. > -The available reset outputs are defined in > -dt-bindings/reset/mt*-resets.h > - > -Example: > - > -infracfg: power-controller@10001000 { > - compatible = "mediatek,mt8173-infracfg", "syscon"; > - reg = <0 0x10001000 0 0x1000>; > - #clock-cells = <1>; > - #reset-cells = <1>; > -}; > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml > new file mode 100644 > index 000000000000..4f43fe9f103e > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml > @@ -0,0 +1,79 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: MediaTek Infrastructure System Configuration Controller > + > +maintainers: > + - Matthias Brugger > + > +description: > + The Mediatek infracfg controller provides various clocks and reset outputs > + to the system. Mention here the headers with clock and reset constants. The same for patches 1 and 2. > + > +properties: > + compatible: > + oneOf: > + - items: > + - enum: > + - mediatek,mt2701-infracfg > + - mediatek,mt2712-infracfg > + - mediatek,mt6765-infracfg > + - mediatek,mt6779-infracfg_ao > + - mediatek,mt6797-infracfg > + - mediatek,mt7622-infracfg > + - mediatek,mt7629-infracfg > + - mediatek,mt7986-infracfg > + - mediatek,mt8135-infracfg > + - mediatek,mt8167-infracfg > + - mediatek,mt8173-infracfg > + - mediatek,mt8183-infracfg > + - mediatek,mt8516-infracfg > + - const: syscon > + - items: > + - const: mediatek,mt7623-infracfg > + - const: mediatek,mt2701-infracfg > + - const: syscon > + > + reg: > + maxItems: 1 > + > + '#clock-cells': > + const: 1 > + > + '#reset-cells': > + const: 1 > + > +required: > + - compatible > + - reg > + - '#clock-cells' > + > +if: > + properties: > + compatible: > + contains: > + enum: > + - mediatek,mt2701-infracfg > + - mediatek,mt2712-infracfg > + - mediatek,mt7622-infracfg > + - mediatek,mt7986-infracfg > + - mediatek,mt8135-infracfg > + - mediatek,mt8173-infracfg > + - mediatek,mt8183-infracfg > +then: > + required: > + - '#reset-cells' > + > +additionalProperties: false > + > +examples: > + - | > + infracfg: syscon@10001000 { reset-controller or clock-controller instead, because syscon is for blocks having only the syscon function. Best regards, Krzysztof